SST32HF1621C 查看數據表（PDF） - Silicon Storage Technology

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SST32HF1621C

Multi-Purpose Flash Plus + SRAM ComboMemory

Silicon Storage Technology 

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

Hardware Block Protection

The SST32HFx1/x1C support bottom hardware block

protection, which protects the bottom 32 KWord block of

the device. The Boot Block address is 000000H-007FFFH.

Program and Erase operations are prevented on the 32

KWord when WP# is low. If WP# is left floating, it is inter-

nally held high via a pull-up resistor, and the Boot Block is

unprotected, enabling Program and Erase operations on

that block.

SRAM Read

The SRAM Read operation of the SST32HFx1/x1C is con-

trolled by OE# and BES1#, both have to be low with WE#

and BES2 high for the system to obtain data from the out-

puts. BES1# and BES2 are used for SRAM bank selection.

OE# is the output control and is used to gate data from the

output pins. The data bus is in high impedance state when

OE# is high. Refer to the Read cycle timing diagram, Fig-

ure 3, for further details.

Hardware Reset (RST#)

The RST# pin provides a hardware method of resetting the

device to read array data. When the RST# pin is held low

for at least TRP, any in-progress operation will terminate and

return to Read mode. When no internal Program/Erase

operation is in progress, a minimum period of TRHR is

required after RST# is driven high before a valid Read can

take place (see Figure 17).

The Erase or Program operation that has been interrupted

needs to be reinitiated after the device resumes normal

operation mode to ensure data integrity.

Flash Software Data Protection (SDP)

The SST32HFx1/x1C provide the JEDEC approved soft-

ware data protection scheme for all flash memory bank

data alteration operations, i.e., Program and Erase. Any

Program operation requires the inclusion of a series of

three-byte sequence. The three byte-load sequence is

used to initiate the Program operation, providing optimal

protection from inadvertent Write operations, e.g., during

the system power-up or power-down. Any Erase operation

requires the inclusion of six-byte load sequence. The

SST32HFx1/x1C devices are shipped with the software

data protection permanently enabled. See Table 5 for the

specific software command codes. During SDP command

sequence, invalid commands will abort the device to Read

mode, within TRC. The contents of DQ15-DQ8 can be VIL or

VIH, but no other value, during any SDP command

sequence.

SRAM Write

The SRAM Write operation of the SST32HFx1/x1C is con-

trolled by WE# and BES1#, both have to be low, BES2

must be high for the system to write to the SRAM. During

the Word-Write operation, the addresses and data are ref-

erenced to the rising edge of either BES1#, WE#, or the

falling edge of BES2 whichever occurs first. The write time

is measured from the last falling edge of BES#1 or WE# or

the rising edge of BES2 to the first rising edge of BES1#, or

WE# or the falling edge of BES2. Refer to the Write cycle

timing diagrams, Figures 4 and 5, for further details.

Product Identification

The Product Identification mode identifies the devices as

the SST32HFx1/x1C and manufacturer as SST. This

mode may be accessed by software operations only.

The hardware device ID Read operation, which is typi-

cally used by programmers, cannot be used on this

device because of the shared lines between flash and

SRAM in the multi-chip package. Therefore, applica-

tion of high voltage to pin A9 may damage this device.

Users may use the software Product Identification opera-

tion to identify the part (i.e., using the device ID) when using

multiple manufacturers in the same socket. For details, see

Tables 4 and 5 for software operation, Figure 14 for the

software ID entry and read timing diagram and Figure 23

for the ID entry command sequence flowchart.

TABLE 2: PRODUCT IDENTIFICATION

Manufacturer’s ID

Device ID

SST32HF16x1x

SST32HF32x1x

Address

0000H

0001H

0001H

Data

BFH

234BH

235BH

T2.2 1236

©2005 Silicon Storage Technology, Inc.

5

S71236-04-000

5/05

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