SST39SF010A-55-4I-WH 查看數據表（PDF） - Silicon Storage Technology

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SST39SF010A-55-4I-WH

1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash

Silicon Storage Technology 

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

ADDRESS AMS-0

CE#

SIX-BYTE CODE FOR CHIP-ERASE

5555 2AAA

5555

5555

2AAA

5555

TSCE

OE#

WE#

TWP

DQ7-0

AA

SW0

55

SW1

80

SW2

AA

SW3

55

SW4

10

SW5

Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are

interchageable as long as minimum timings are met. (See Table 10)

SAX = Sector Address

AMS = Most significant address

AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040

FIGURE 11: WE# Controlled Chip-Erase Timing Diagram

1147 F17.1

ADDRESS A14-0

CE#

OE#

WE#

DQ7-0

Three-byte Sequence for

Software ID Entry

5555

2AAA

5555

0000

0001

TWP

TIDA

TWPH

AA

55

90

TAA

BF

Device ID

SW0

SW1

SW2

Device ID = B5H for SST39SF010A, B6H for SST39SF020A, and B7H for SST39SF040

1147 F09.2

FIGURE 12: Software ID Entry and Read

©2010 Silicon Storage Technology, Inc.

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