PIC16LC72-10I/SS 查看數據表（PDF） - Microchip Technology

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PIC16LC72-10I/SS

8-Bit CMOS Microcontrollers with A/D Converter

Microchip Technology 

PIC16C7X

FIGURE 4-3: PIC16C76/77 PROGRAM

MEMORY MAP AND STACK

PC<12:0>

CALL, RETURN

13

RETFIE, RETLW

Stack Level 1

Stack Level 2

Stack Level 8

Reset Vector

0000h

Interrupt Vector

On-Chip Page 0

On-Chip Page 1

On-Chip Page 2

On-Chip Page 3

0004h

0005h

07FFh

0800h

0FFFh

1000h

17FFh

1800h

1FFFh

4.2 Data Memory Organization

Applicable Devices

72 73 73A 74 74A 76 77

The data memory is partitioned into multiple banks

which contain the General Purpose Registers and the

Special Function Registers. Bits RP1 and RP0 are the

bank select bits.

RP1:RP0 (STATUS<6:5>)

= 00 → Bank0

= 01 → Bank1

= 10 → Bank2

= 11 → Bank3

Each bank extends up to 7Fh (128 bytes). The lower

locations of each bank are reserved for the Special

Function Registers. Above the Special Function Regis-

ters are General Purpose Registers, implemented as

static RAM. All implemented banks contain special

function registers. Some “high use” special function

registers from one bank may be mirrored in another

bank for code reduction and quicker access.

4.2.1 GENERAL PURPOSE REGISTER FILE

The register file can be accessed either directly, or indi-

rectly through the File Select Register FSR

(Section 4.5).

DS30390E-page 20

© 1997 Microchip Technology Inc.

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