ST72F340S4T6 查看數據表（PDF） - STMicroelectronics

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ST72F340S4T6

8-BIT MCU WITH UP TO 16K FLASH MEMORY, 10-BIT ADC, TWO 16-BIT TIMERS, TWO I2C, SPI, SCI

STMicroelectronics 

ST72340, ST72344, ST72345

DATA EEPROM (Cont’d)

5.4 POWER SAVING MODES

Wait mode

The DATA EEPROM can enter WAIT mode on ex-

ecution of the WFI instruction of the microcontrol-

ler or when the microcontroller enters Active Halt

mode.The DATA EEPROM will immediately enter

this mode if there is no programming in progress,

otherwise the DATA EEPROM will finish the cycle

and then enter WAIT mode.

Active Halt mode

Refer to Wait mode.

Halt mode

The DATA EEPROM immediately enters HALT

mode if the microcontroller executes the HALT in-

struction. Therefore the EEPROM will stop the

function in progress, and data may be corrupted.

5.5 ACCESS ERROR HANDLING

If a read access occurs while E2LAT = 1, then the

data bus will not be driven.

If a write access occurs while E2LAT = 0, then the

data on the bus will not be latched.

If a programming cycle is interrupted (by RESET

action), the integrity of the data in memory will not

be guaranteed.

5.6 DATA EEPROM READ-OUT PROTECTION

The read-out protection is enabled through an op-

tion bit (see option byte section).

When this option is selected, the programs and

data stored in the EEPROM memory are protected

against read-out (including a re-write protection).

In Flash devices, when this protection is removed

by reprogramming the Option Byte, the entire Pro-

gram memory and EEPROM is first automatically

erased.

Note: Both Program Memory and data EEPROM

are protected using the same option bit.

Figure 10. Data EEPROM Programming Cycle

INTERNAL

PROGRAMMING

VOLTAGE

WRITE OF

DATA

LATCHES

READ OPERATION NOT POSSIBLE

ERASE CYCLE

WRITE CYCLE

tPROG

ALL INTERRUPTS MUST BE MASKED 1)

Note 1: refer to “Programming of EEPROM data” on page 189

READ OPERATION POSSIBLE

E2LAT

E2PGM

I bit in CC register

21/191

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