ST72F521AR9TC 查看數據表（PDF） - STMicroelectronics

零件编号

产品描述 (功能)

生产厂家

ST72F521AR9TC

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE

STMicroelectronics 

ST72521

Address

Block

Register

Label

Register Name

Reset

Status

Remarks

0050h

0051h

0052h

0053h

0054h

0055h

0056h

0057h

0058h

0059h

005Ah

005Bh

005Ch

005Dh

005Eh

005Fh

0060h

to

006Fh

0070h

0071h

0072h

0073h

0074h

0075h

0076h

0077h

0078h

0079h

007Ah

007Bh

007Ch

007Dh

007Eh

007Fh

SCISR

SCI Status Register

C0h Read Only

SCIDR

SCI Data Register

xxh

R/W

SCIBRR

SCI Baud Rate Register

00h

R/W

SCI

SCICR1

SCICR2

SCI Control Register 1

SCI Control Register 2

x000 0000b R/W

00h

R/W

SCIERPR SCI Extended Receive Prescaler Register

00h

R/W

Reserved area

---

SCIETPR SCI Extended Transmit Prescaler Register

00h

R/W

Reserved Area (2 Bytes)

CAN

CANISR

CANICR

CANCSR

CANBRPR

CANBTR

CANPSR

CAN Interrupt Status Register

CAN Interrupt Control Register

CAN Control / Status Register

CAN Baud Rate Prescaler Register

CAN Bit Timing Register

CAN Page Selection Register

First address

to

Last address of CAN page x

00h

R/W

00h

R/W

00h

R/W

00h

R/W

23h

R/W

00h

R/W

--

See CAN

Description

ADC

ADCCSR

ADCDRH

ADCDRL

Control/Status Register

Data High Register

Data Low Register

00h

R/W

00h

Read Only

00h

Read Only

PWMDCR3 PWM AR Timer Duty Cycle Register 3

00h

R/W

PWMDCR2 PWM AR Timer Duty Cycle Register 2

00h

R/W

PWMDCR1 PWM AR Timer Duty Cycle Register 1

00h

R/W

PWMDCR0 PWM AR Timer Duty Cycle Register 0

00h

R/W

PWMCR

PWM AR Timer Control Register

00h

R/W

PWM ART ARTCSR Auto-Reload Timer Control/Status Register

00h

R/W

ARTCAR Auto-Reload Timer Counter Access Register

00h

R/W

ARTARR Auto-Reload Timer Auto-Reload Register

00h

R/W

ARTICCSR AR Timer Input Capture Control/Status Reg.

00h

R/W

ARTICR1 AR Timer Input Capture Register 1

00h

Read Only

ARTICR2 AR Timer Input Capture Register 1

00h

Read Only

Reserved Area (2 Bytes)

Legend: x=undefined, R/W=read/write

Notes:

1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-

tion, the values of the I/O pins are returned instead of the DR register contents.

2. The bits associated with unavailable pins must always keep their reset value.

17/211

Share Link: