STA328 查看數據表（PDF） - STMicroelectronics

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STA328

2.1-channel high-efficiency digital audio system

STMicroelectronics 

Description

STA328

1.2

EQ processing

Two channels of input data (re-sampled if necessary) at 96 kHz are provided to the EQ

processing block. In this block, up to four user-defined biquads can be applied to each of the

two channels.

Pre-scaling, DC-blocking, high-pass, de-emphasis, bass, and tone control filters can also be

applied based on various configuration parameter settings.

The entire EQ block can be bypassed for all channels simultaneously by setting the DSPB

bit to 1. And the CxEQBP bits can be used to bypass the EQ function on a per channel

basis. Figure 3 shows the internal signal flow through the EQ block.

Figure 3. Channel signal flow through the EQ block

Re-sampled

Input

Pre

Scale

High-P ass

Filt er

BQ#1

BQ#2

BQ#3

BQ#4

De-

Emphasis

If HPB = 0

4 Biquads

User defined if AMEQ = 00

Preset EQ if AMEQ = 01

Auto Loudness if AMEQ = 10

If DEMP = 1

Bass

Filt er

T reble

Filt er

To

Mix

If CxT CB = 0

BT C: Bass Boost/Cut

T T C: T reble Boost/Cut

If DSPB = 0 & CxEQB = 0

1.3

6/57

Output configurations

Figure 4. Output power-stage configurations

Half

Bridge

Half

Bridge

Half

Bridge

Half

Bridge

OUT1A

OUT1B

OUT2A

OUT2B

Channel 1

2-channel (full-bridge) configuration,

register bits OCFG[1:0] = 00

Channel 2

Half

Bridge

Half

Bridge

Half

Bridge

Half

Bridge

OUT1A

OUT1B

OUT2A

OUT2B

Channel 1

Channel 2

2.1-channel configuration,

register bits OCFG[1:0] = 01

Channel 3

Half

Bridge

Half

Bridge

Half

Bridge

Half

Bridge

OUT1A

OUT1B

OUT2A

OUT2B

Channel 3

1-channel mono-parallel configuration,

register bits OCFG[1:0] = 11

The setup register is Configuration register

F (addr 0x05) on page 31

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