STK16CA8 查看數據表（PDF） - Simtek Corporation
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STK16CA8 Datasheet PDF : 12 Pages
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SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
#1, #2
Alt.
PARAMETER
1
tELQV
2
tAVAVf
3
tAVQVg
4
tGLQV
5
tAXQXg
6
tELQX
7
tEHQZh
8
tGLQX
9
tGHQZh
10
tELICCHe
11
tEHICCLe
tACS
tRC
tAA
tOE
tOH
tLZ
tHZ
tOLZ
tOHZ
tPA
tPS
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
Note f: W must be high during SRAM READ cycles.
Note g: Device is continuously selected with E and G both low.
Note h: Measured ± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledf, g
ADDRESS
DQ (DATA OUT)
5
tAXQX
2
tAVAV
3
tAVQV
SRAM READ CYCLE #2: E Controlledf
ADDRESS
E
6
tELQX
2
tAVAV
1
tELQV
G
DQ (DATA OUT)
ICC
8
tGLQX
4
tGLQV
10
tELICCH
STANDBY
ACTIVE
STK16CA8
(VCC = 3.0V +20%, -10%)
STK16CA8-25
MIN MAX
STK16CA8-35
MIN MAX
STK16CA8-45
UNITS
MIN MAX
25
35
45
ns
25
35
45
ns
25
35
45
ns
10
15
20
ns
3
3
3
ns
3
3
3
ns
10
13
15
ns
0
0
0
ns
10
13
15
ns
0
0
0
ns
25
35
45
ns
DATA VALID
11
tEHICCL
7
tEHQZ
9
tGHQZ
DATA VALID
September 2003
3 Document Control # ML0023 rev 0.1
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