MT8841 查看數據表（PDF） - Mitel Networks
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MT8841 Datasheet PDF : 10 Pages
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MT8841
IN+ 1
IN- 2
GS 3
VRef 4
CAP 5
OSC1 6
OSC2 7
VSS 8
16 VDD
15 IC2
14 IC1
13 PWDN
12 CD
11 DR
10 DATA
9 DCLK
16 PIN PLASTIC DIP/SOIC
IN+
IN-
GS
VRef
CAP
NC
OSC1
NC
OSC2
VSS
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
20 PIN SSOP
VDD
IC2
NC
NC
IC1
PWDN
CD
DR
DATA
DCLK
Pin Description
Figure 2 - Pin Connections
Pin #
Name
16 20
Description
1 1 IN+ Non-inverting Op-Amp (Input).
2 2 IN- Inverting Op-Amp (Input).
3 3 GS Gain Select (Output). Gives access to op-amp output for connection of feedback resistor.
4 4 VRef Voltage Reference (Output). Nominally VDD/2. This is used to bias the op-amp inputs.
5 5 CAP Capacitor. Connect a 0.1µF capacitor to VSS.
6 7 OSC1 Oscillator (Input). Crystal or ceramic resonator connection. This pin can be driven directly
from an external clocking source.
7 9 OSC2 Oscillator (Output). Crystal or ceramic resonator connection. When OSC1 is driven by an
external clock, this pin should be left open.
8 10 VSS Power supply ground.
9 11 DCLK Data Clock (Output). Outputs a clock burst of 8 low going pulses at 1202.8Hz (3.5795MHz
divided by 2976). Every clock burst is initiated by the DATA stop bit start bit sequence. When
the input DATA is 1202.8 baud, the positive edge of each DCLK pulse coincides with the
middle of the data bits output at the DATA pin. No DCLK pulses are generated during the start
or stop bits. Typically, DCLK is used to clock the eight data bits from the 10 bit data word into a
serial-to-parallel converter.
10 12
DATA
Data (Output). Serial data output corresponding to the FSK input and switching at the input
baud rate. Mark frequency at the input corresponds to a logic high, while space frequency
corresponds to a logic low at the DATA output. With no FSK input, DATA is at logic high. This
output stays high until CD has become active.
11 13
DR Data Ready (Open Drain Output). This output goes low after the last DCLK pulse of each
word. This can be used to identify the data (8-bit word) boundary on the serial output stream.
Typically, DR is used to latch the eight data bits from the serial-to-parallel converter into a
microcontroller.
12 14
CD Carrier Detect (Open Drain Output). A logic low indicates that a carrier has been present for
a specified time on the line. A time hysteresis is provided to allow for momentary discontinuity
of carrier.
13 15 PWDN Power Down (Input). Active high, Schmitt Trigger input. Powers down the device including the
input op-amp and the oscillator.
14 16
15 19
IC1 Internal Connection 1. Connect to VSS.
IC2 Internal Connection 2. Internally connected, leave open circuit.
16 20
6,8
17,
18
VDD Positive power supply voltage.
NC No Connection.
5-12
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