TB2118 查看數據表（PDF） - Toshiba

零件编号

产品描述 (功能)

生产厂家

TB2118

High Speed PLL For DTS (Bi−CMOS Integrated Circuit Silicon Monolithic)

Toshiba 

TB2118F

3. Setting programmable counter block

1) Circuit configuration

The progammable counter block consists of a 2-modulus prescaler, 4-bit swallow counter, and 12-bit

programmable binary counter.

FM VCO 15

AM VCO 16

PSC

(MODE, AM / PM)

X

2 − modulus

prescaler

(AM)

(FM)

4 − bit (P00 to P03)

swallow counter

PRS

12 − bit (P04 to P15)

programmable binary counter

fSIG

To phase

comparator

2) Setting input pin / dividing mode (AM / FM, mode)

AM / FM

0

1

Mode

0

1

Input Pin

FMVCO

AMVCO

Input Frequency

30~150MHz

1~40MHz

Divided Frequency

528~65.535

3) Setting divided frequency (P00 to P15)

· By pulse swallow (in FW or SW mode), n = 528 to 65.535

LSB

MSB

Dividing Mode

By pulse swallow

(16-bit)

20

215

10

2002-10-30

Share Link: