M80C186 查看數據表（PDF） - Intel

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M80C186

CHMOS HIGH INTEGRATION 16-BIT MICROPROCESSOR

Intel 

M80C186

Enhanced Mode Operation

In Enhanced Mode the M80C186 will operate with

Power-Save DRAM refresh and numerics coproc-

essor support in addition to all the Compatible Mode

features

In Compatible Mode the M80C186 operates with all

the features of the NMOS M80186 with the excep-

tion of M8087 support (i e no numeric coprocessing

is possible in Compatible Mode) Queue-Status in-

formation is still available for design purposes other

than M8087 support

All the Enhanced Mode features are completely

masked when in Compatible Mode A write to any of

the Enhanced Mode registers will have no effect

while a read will not return any valid data

Entering Enhanced Mode

If connected to a numerics coprocessor this mode

will be invoked automatically Without a NPX this

mode can be entered by tying the RESET output

signal from the M80C186 to the TEST BUSY input

Queue-Status Mode

The queue-status mode is entered by strapping the

RD pin low RD is sampled at RESET and if LOW

the M80C186 will reconfigure the ALE and WR pins

to be QS0 and QS1 respectively This mode is avail-

able on the M80C186 in both Compatible and En-

hanced Modes and is identical to the NMOS

M80186

DRAM Refresh Control Unit

Description

The Refresh Control Unit (RCU) automatically gen-

erates DRAM refresh bus cycles The RCU operates

only in Enhanced Mode After a programmable peri-

od of time the RCU generates a memory read re-

quest to the BIU If the address generated during a

refresh bus cycle is within the range of a properly

programmed chip select that chip select will be acti-

vated when the BIU executes the refresh bus cycle

The ready logic and wait states programmed for that

region will also be in force If no chip select is acti-

vated then external ready is automatically required

to terminate the refresh bus cycle

If the HLDA pin is active when a DRAM refresh re-

quest is generated (indicating a bus hold condition)

then the M80C186 will deactivate the HLDA pin in

order to perform a refresh cycle The circuit external

to the M80C186 must remove the HOLD signal in

order to execute the refresh cycle The sequence of

HLDA going inactive while HOLD is being held active

can be used to signal a pending refresh request

All registers controlling DRAM refresh may be read

and written in Enhanced Mode When the processor

is operating in Compatible Mode they are deselect-

ed and are therefore inaccessible Some fields of

these registers cannot be written and are always

read as zeros

DRAM Refresh Addresses

The address generated during a refresh cycle is de-

termined by the contents of the MDRAM register

(see Figure 40) and the contents of a 9-bit counter

Figure 41 illustrates the origin of each bit

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MDRAM M6 M5 M4 M3 M2 M1 M0 0 0 0 0 0 0 0 0 0

Offset E0H

Bits 0–8 Reserved read back as 0

Bits 9–15 M0– M6 are address bits A13–A19 of the 20-bit memory refresh address These bits should

correspond to the chip select address to be activated for the DRAM partition These bits are

set to 0 on RESET

Figure 40 Memory Partition Register

A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

M6 M5 M4 M3 M2 M1 M0 0 0 0 CA8 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 1

M6–M0 Bits defined by MDRAM Register

CA8–CA0 Bits defined by refresh address counter

Figure 41 Addresses Generated by RCU

41

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