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TDA1566J 查看數據表(PDF) - NXP Semiconductors.

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TDA1566J Datasheet PDF : 46 Pages
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NXP Semiconductors
TDA1566
I2C-bus controlled dual channel/single channel amplifier
Table 20. Start-up and shutdown timing in I2C-bus mode …continued
Step Action
Result
3
SVR voltage has become larger than VP / 2 resulting in
setting DB3[D4]
4
TDA1566 is switched from DIAG is pulled LOW
operating to standby with
IB1[D0] = 0
SVR is discharged, OUTx voltage tracks SVR voltage
amplifier is slow muted
5
SVR voltage has dropped below VP / 2 resulting in
resetting DB3[D4]
6
TDA1566 is switched from see step 2
standby to operating with
IB1[D0] = 1
7
see step 3
8
TDA1566 is disabled with DIAG is pulled LOW
EN
amplifier is fast muted
SVR is discharged, OUTx voltage tracks SVR voltage
9
see step 5
10
OUTx is at ground potential, DIAG is released, TDA1566 is
off
6.5.2 Engine start
The DC-output voltage of the amplifier follows the voltage on the SVR pin. On the SVR pin
a capacitor is connected which is used for start-up and shutdown timing as well as for DC
load detection. If the supply voltage drops during engine start below 8.6 V the SVR
capacitor will be discharged and the fast mute is activated to prevent audible transients at
the output.
If in I2C-bus mode the supply voltage drops below 5.5 V (see VP(POR)) the content of the
I2C-bus latches cannot be guaranteed and the power-on reset will be activated:
DB3[D7] = 1. All latches will be reset, the amplifier is switched off and the DIAG pin will be
pulled LOW to indicate that a power-on reset has occurred. The TDA1566 will not start-up
but wait for a command to start-up.
7. Limiting values
Table 21. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
VP
supply voltage
operating; RL = 4
operating; RL = 2 or
1
non operating
VP(r)
IOSM
reverse supply voltage
non-repetitive peak output current
load dump protection;
during 50 ms;
tr 2.5 ms
maximum 10 minutes
Min
Max
Unit
-
18
V
-
16
V
1
+50
V
-
50
V
-
2
V
-
13
A
TDA1566_2
Product data sheet
Rev. 02 — 20 August 2007
© NXP B.V. 2007. All rights reserved.
19 of 46

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