Philips Semiconductors
Low dropout voltage/quiescent current 5 V
voltage regulator with enable
Preliminary specification
TDA3674
CHARACTERISTICS
VP = 14.4 V; Tamb = 25 °C; measured in test circuit of Fig.3; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Supply voltage: pin VP
VP
supply voltage
TDA3674T
TDA3674AT
Iq
quiescent current
Enable input: pin EN
regulator operating; note 1
VP = 14.4 V; IREG = 0 mA;
VI(EN) = 0 V
VP = 14.4 V; IREG = 0 mA;
VI(EN) = 5 V
6 V ≤ VP ≤ 22 V; IREG = 10 mA
6 V ≤ VP ≤ 22 V; IREG = 50 mA
3
14.4 33 V
3
14.4 45 V
−
4
15 µA
−
15 30 µA
−
0.2 0.5 mA
−
1.4 2.5 mA
VI(EN)
enable input voltage
II(EN)
enable input current
Regulator output: pin REG; note 2
enable off; VREG ≤ 0.8 V
enable on; VREG ≥ 4.5 V
VI(EN) = 5 V
−1 −
+1.0 V
3.0 −
18 V
−
0.3 −
µA
VREG
VREG(drop)
VREG(stab)
∆VREG(line)
∆VREG(load)
output voltage
dropout voltage
long-term stability
line input regulation voltage
load output regulation
voltage
8 V ≤ VP ≤ 22 V; IREG = 0.5 mA
8 V ≤ VP ≤ 22 V; IREG = 0.5 mA;
Tamb ≤ 125 °C
0.5 mA ≤ IREG ≤ 100 mA
6 V ≤ VP ≤ 45 V; IREG = 0.5 mA
VP = 4.5 V; Tamb ≤ 85 °C;
IREG = 50 mA
8 V ≤ VP ≤ 16 V; IREG = 0.5 mA
7 V ≤ VP ≤ 22 V; IREG = 0.5 mA
7 V ≤ VP ≤ 45 V
0.5 mA ≤ IREG ≤ 50 mA
SVRR
IREG(crl)
ILO(rp)
supply voltage ripple
rejection
current limit
output leakage current at
reverse polarity
fi = 120 Hz; Vi(ripple) = 1 V (RMS);
IREG = 0.5 mA
VREG > 4.5 V
VP = −15 V; VREG ≤ 0.3 V
4.8 5.0
4.75 5.0
5.2 V
5.25 V
4.75 5.0 5.25 V
4.75 5.0 5.25 V
−
0.18 0.3 V
−
20 −
mV/1000 h
−
1
10 mV
−
1
30 mV
−
1
50 mV
−
10 50 mV
50 60 −
dB
0.13 0.25 −
A
−
1
500 µA
Notes
1. The regulator output will follow VP if VP < VREG + VREG(drop).
2. Limiting values as applicable for device type:
a) TDA3674T: VP ≤ 33 V, −40 °C ≤ Tamb ≤ +85 °C.
b) TDA3674AT: VP ≤ 45 V, −40 °C ≤ Tamb ≤ +125 °C.
2000 Feb 01
5