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TDA5360UK

Pre–Amplifier for Hard Disk Drive with MR-Read / Inductive Write Heads

Philips Electronics 

Philips Semiconductors

Pre-Amplifier for Hard Disk Drive with

MR-Read / Inductive Write Heads

Objective Specification, Revision 2.2

TDA5360

10.5 Serial Interface Operations

The serial interface communication consists of an adress word of 8 bits followed by a data word of 8 bits. See section

11, page 24 and 25 for timing diagrams.

10.5.1 SERIAL ADDRESSING

When SEN goes HIGH, bits are latched-in at rising edges of SCLK. The first eight bits a7-a0 starting with the LSB, are

shifted serially into an address register.

If SEN goes LOW before 16 bits have been found, then the operation is ignored.

When STWn is HIGH; if a1 does not match CS0 or a2 does not match CS1, then the operation is ignored.

When STWn is LOW; if a1 and a2 are not HIGH, then the operation is ignored.

Bits a3 to a6 constitute the register address. Bit a7 is an unused one.

If

(a0, a1, a2, STWn) = (0, CS0, CS1, 1)

or if (a0, a1, a2, STWn) = (0, 1, 1, 0)

then a PROGRAMMING sequence starts (see Reg. 09 description for details about preamp addressing)

If

(a0, a1, a2, STWn) = (1, CS0, CS1, 1)

or if (a0, a1, a2, STWn) = (1, 1, 1, 0)

then READING data from the pre-amplifier can start. The data read back can be either 3.3V compatible or 5V

compatible depending on SIOLV bit in Reg. 09.

10.5.2 PROGRAMMING DATA

During a programming sequence, the last eight bits d0-d7, before SEN goes LOW, are shifted into an input register.

When SEN goes LOW, the communication sequence is ended and the data in the input register are copied in parallel to

the data register corresponding to the decoded address a6-a3. SEN should go LOW at least 5ns after the last rising

edge of SCLK.

10.5.3 READING DATA

Immediately after the IC detects a reading sequence, data from the data register (address a6-a3) are copied

in parallel to the input register. The LSB d0 is placed on SDATA line followed by d1 at the

next falling edge of SCLK, etc...

If SEN goes LOW before 8 address bits (a7-a0) have been detected, the communication is ignored. If SEN goes LOW

before the 8 data bits have been sent out of the IC, the reading sequence is immediately interrupted.

SEN must stay LOW at least 75ns between two adressings.

See Timing diagramms for Serial Adressing on section 11.

10.5.4 BROADCAST MODE

When A1=A2=1 and STWN=LOW, all the preamps will be adressed whatever their CS1/CS0 setup is.

This mode allows parallel programming of any register of the serial interface, and allows STW mode programming (See

Reg. 09 description).

1998 July 30

16

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