TDA7333 查看數據表（PDF） - STMicroelectronics

零件编号

产品描述 (功能)

生产厂家

TDA7333

RDS/RBDS processor

STMicroelectronics 

TDA7333N

Functional description

The second diagram gives information about the flywheel counter status. The counter value

could be between 0 and 63.

The next two charts showing the bits “synch” rds_int[4] and “data_ok” rds_corrp[1] (refer to

Section 3.8.1 and Section 3.8.3).

The last graph indicates every generated buffer not empty (bne) interrupt. After each

interrupt the RDS data will be read out from the RAM buffer (within 22 ms), before next RDS

block is written into. This is done to reset the interrupt flag “int” rds_int[0] each time. Further

the “syncw” bit rds_bd_ctrl[0] is set to one, to store only synchronized RDS blocks (refer to

Section 3.8.6).

The following case is considered now: First the receiving condition is good (section 1), then

it is going to be worse (section 2) because of entering a tunnel, after leaving it is going to be

better again (section 3).

Section 1: After power up or resynchronization (“ar_res”, rds_int[5]), the first recognized

RDS block is stored in the RAM buffer and generates an “bne” interrupt. At

the same time “synch” bit rds_int[4] is set to one. With the next stored RDS

block the “data_ok” bit rds_corrp[1] is set, because the flywheel counter

becomes greater than two. With every next RDS block the flywheel counter

increments by two, until the upper margin of 63 is reached.

Section 2: Because of entering a tunnel, the demodulator increases bad marked RDS

bits until all are marked as bad. The flywheel counter decrements by one

after each new RDS block because of error corrections done on good

marked RDS bits or because the syndrome of the expected block was not

zero after error correction. The “data_ok” bit rds_corrp[1] is set to zero

whenever the flywheel counter decrements. Note that the synchronization

flag “synch” rds_int[4] is set and the interrupt is performed after every

expected RDS block, until the flywheel counter is zero. Then the RDS is

desynchronized. Now spurious interrupts could occur because of random

RDS blocks detected during resynchronization process. If the time of

receiving bad signal is shorter than the decreasing time of the flywheel

counter, then the RDS will keep its synchronization and stores RDS data

every 22 ms.

Section 3: After leaving the tunnel, the signal is getting better and the RDS will be

synchronized again as described in section 1.

3.7

RAM Buffer

The RAM buffer can store up to 24 RDS blocks (rds_bd_h[7:0] and rds_bd_l[7:0]) with their

related information (rds_qu[7:0] and rds_corrp[7:0]) (Figure 7):

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