TDA8376 查看數據表（PDF） - Philips Electronics

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TDA8376

I²C-bus controlled PAL/NTSC TV processors

Philips Electronics 

Philips Semiconductors

I2C-bus controlled PAL/NTSC TV processors

Objective specification

TDA8376; TDA8376A

8.2.1 INPUT CONTROL BITS

Table 3 Source select 1

INA

INB

DECODER AND TXT

0

0

CVBSINT

0

1

CVBSEXT

1

0 S-VHS

1

1 S-VHS (CVBSEXT)

Table 4 Source select 2

INC

IND

PIP

0

0

CVBSINT

0

1

CVBSEXT

1

0 S-VHS

1

1 S-VHS (CVBSEXT)

Table 5 Phase 1 (ϕ1) time constant

FOA FOB

MODE

0

0 normal

0

1 slow

1

X(1) fast

Note

1. X = don’t care.

Table 6 Crystal indication XA and XB

XA

XB

CRYSTAL

0

0 two 3.6 MHz

0

1 one 3.6 MHz (pin 33)

1

0 one 4.4 MHz (pin 34)

1

1 3.6 MHz (pin 33) and

4.4 MHz (pin 34)

Table 7 Forced field frequency

FORF

0

0

1

1

FORS

0

1

0

1

FIELD FREQUENCY

auto (60 Hz when line not

synchronized)

60 Hz; note 1

50 Hz; note 1

auto

(50 Hz when line not synchronized)

Note

1. When the forced mode is selected the divider will only

switch to that position when the horizontal oscillator is

not synchronized.

Table 8 Interlace

DL

0 interlace

1 de-interlace

STATUS

Table 9 Standby

STB

0

1

standby

normal

MODE

Table 10 Synchronization mode

POC

0

1

active

not active

MODE

Table 11 Colour decoder mode

CM2

0

0

0

0

1

1

1

1

CM1

0

0

1

1

0

0

1

1

CM0

DECODER MODE

0 not forced, own intelligence

1 forced NTSC 3.6 MHz

0 forced PAL 4.4 MHz

1 forced SECAM

0 forced NTSC 4.4 MHz

1 forced PAL 3.6 MHz (pin 33)

0 forced PAL 3.6 MHz (pin 34)

1 no function

1996 Jan 26

14

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