TDA8024T/C1 查看數據表（PDF） - NXP Semiconductors.
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TDA8024T/C1 Datasheet PDF : 33 Pages
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NXP Semiconductors
TDA8024
Standard smart card interface
8.2 Voltage supervisor
8.2.1 Without external divider on pin PORADJ (or with TDA8024AT)
The voltage supervisor surveys the VDD supply. A defined reset pulse of approximately
8 ms (tW) is used internally to keep the IC inactive during power-on or power-off of the VDD
supply (see Figure 5).
As long as VDD is less than Vth2 + Vhys2, the IC remains inactive whatever the levels on the
command lines. This state also lasts for the duration of tW after VDD has reached a level
higher than Vth2 + Vhys2.
When VDD falls below Vth2, a deactivation sequence of the contacts is performed.
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8.2.2 With an external divider on pin PORADJ (not for the TDA8024AT)
If an external resistor bridge is connected to pin PORADJ (R1 and R2 in Figure 1), then
the following occurs:
• The internal threshold voltage Vth2 is overridden by the external voltage and by the
hysteresis, therefore:
Vth2extrise
=
1
+
RR-----12-
Vbr
i
dg
e
+
-V---h---y--2s----e---x--t-
Vth2extfall
=
1 + RR-----12-
V
brid
ge
–
-V---h---y--2s----e---x--t-
where Vbridge = 1.25 V typ. and Vhys(ext) = 60 mV typ.
• The reset pulse width tW is doubled to approximately 16 ms.
Input PORADJ is biased internally with a pull-down current source of 4 A which is
removed when the voltage on pin PORADJ exceeds 1 V. This ensures that after detection
of the external bridge by the IC during power-on, the input current on pin PORADJ does
not cause inaccuracy of the bridge voltage.
The minimum threshold voltage should be higher than 2 V.
The maximum threshold voltage may be up to VDD.
TDA8024
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4.0 — 3 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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