NXP Semiconductors
TDA8933B
Class D audio amplifier
SE configuration:
Po(0.5%) = -------R--------L--------+----------R-------D--------S-----o-----n-R-------+-L---------R--------s------+----------R--------E------S-----8R------×---×--R--(--L-1----–-----t--w---(--m----i-n---)---×------f--o---s--c--)----×----V-----P------2
(2)
BTL configuration:
Po(0.5%) = -------R--------L--------+---------2----------×---------(-----RR-------L-D-------S-----o------n-------+----------R--------s-----)--2-----×-×----R-(--1-L---–-----t--w---(--m----i-n---)---×------f--o---s--c---)---×-----V----P------2
(3)
Where:
• VP = supply voltage VDDP1 − VSSP1 (V) or VDDP2 − VSSP2 (V)
• RL = load resistance (Ω)
• RDSon = drain-source on-state resistance (Ω)
• Rs = series resistance output inductor (Ω)
• RESR = Equivalent Series Resistance SE capacitance (Ω)
• tw(min) = minimum pulse width(s); 80 ns typical
• fosc = oscillator frequency (Hz); 320 kHz typical with Rosc = 39 kΩ
The output power Po at THD+N = 10 % can be estimated by:
Po(10%) = 1.25 × Po(0.5%)
(4)
Figure 7 and Figure 8 show the estimated output power at THD+N = 0.5 % and
THD+N = 10 % as a function of the supply voltage for SE and BTL configurations at
different load impedances. The output power is calculated with: RDSon = 0.38 Ω (at
Tj = 25 °C), Rs = 0.05 Ω, RESR = 0.05 Ω and IO(ocp) = 2 A (minimum).
TDA8933B_1
Preliminary data sheet
Rev. 01 — 23 October 2008
© NXP B.V. 2008. All rights reserved.
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