LD87C52-1 查看數據表（PDF） - Intel
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LD87C52-1 Datasheet PDF : 23 Pages
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8XC52 54 58
PROGRAMMING THE EPROM
The part must be running with a 4 MHz to 6 MHz
oscillator The address of an EPROM location to be
programmed is applied to address lines while the
code byte to be programmed in that location is ap-
plied to data lines Control and program signals must
be held at the levels indicated in Table 4 Normally
EA VPP is held at logic high until just before ALE
PROG is to be pulsed The EA VPP is raised to VPP
ALE PROG is pulsed low and then EA VPP is re-
turned to a high (also refer to timing diagrams)
DEFINITION OF TERMS
ADDRESS LINES P1 0 – P1 7 P2 0 – P2 5 respec-
tively for A0 – A13
DATA LINES P0 0 – P0 7 for D0 – D7
CONTROL SIGNALS RST PSEN P2 6 P2 7 P3 3
P3 6 P3 7
PROGRAM SIGNALS ALE PROG EA VPP
NOTES
Exceeding the VPP maximum for any amount of
time could damage the device permanently The
VPP source must be well regulated and free of
glitches
Mode
Program Code Data
Verify Code Data
Program Encryption
Array Address 0– 3FH
Program Lock
Bits
Bit 1
Bit 2
Bit 3
Read Signature Byte
Table 4 EPROM Programming Modes
RST
H
PSEN
L
ALE
PROG
EA
VPP
12 75V
P2 6
L
P2 7
H
H
L
H
H
L
L
H
L
12 75V L
H
H
L
H
L
H
L
H
L
12 75V H
H
12 75V H
H
12 75V H
L
H
H
L
L
P3 3
H
L
H
H
H
H
L
P3 6
H
H
L
H
L
H
L
P3 7
H
H
H
H
L
L
L
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