CXP80720BQ 查看數據表（PDF） - Sony Semiconductor

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CXP80720BQ

CMOS 8-bit Single Chip Microcomputer

Sony Semiconductor 

CXP80712B/80716B/80720B/80724B

(4) Interruption, reset input

Item

External interruption

High and Low level widths

Reset input Low level width

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)

Symbol Pins Conditions Min. Max. Unit

INT0

tIH

tIL

INT1

INT2

NMI

PJ0 to PJ7

tRSL

RST

1

µs

32/fc

µs

Fig. 7. Interruption input timing

INT0

INT1

INT2

NMI

PJ0 to PJ7

(During standby release input)

(Falling edge)

tIH

0.8VDD

tIL

0.2VDD

Fig. 8. Reset input timing

tRSL

RST

0.2VDD

(5) Others

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)

Item

CFG input

High and Low level widths

Symbol

tCFH

tCFL

Pins

CFG

Conditions

Min.

tFRC × 24 + 200

Max. Unit

ns

DFG input

tDFH

High and Low level widths tDFL

DFG

tFRC × 8 + 200

ns

DPG minimum pulse width tDPW

DPG

50

ns

DPG minimum

removal time

trem

DPG

50

ns

PBCTL input

tCTH

High and Low level widths tCTL

PBCTL tsys = 2000/fc

tFRC × 8 + 200 + tsys

ns

EXI input

tEIH

High and Low level widths tEIL

EXI0

EXI1

tsys = 2000/fc

tFRC × 8 + 200 + tsys

ns

Note) tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper 2

bits (CPU clock selection).

tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

tFRC [ns] = 1000/fc

– 20 –

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