TSC80C51TXXX-20AI 查看數據表（PDF） - Temic Semiconductors

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TSC80C51TXXX-20AI

CMOS 0 to 44 MHz Single-Chip 8 Bit Microcontroller

Temic Semiconductors 

TSC80C31/80C51

Idle ICC is measured with all output pins disconnected ;

XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL =

VSS + 0.5 V, VIH = VCC – 0.5 V ; XTAL2 N.C ; Port 0 =

VCC ; EA = RST = VSS.

Power Down ICC is measured with all output pins

disconnected ; EA = PORT 0 = VCC ; XTAL2 N.C. ;

RST = VSS.

Note 2 : Capacitance loading on Ports 0 and 2 may cause

spurious noise pulses to be superimposed on the VOLS of

ALE and Ports 1 and 3. The noise is due to external bus

capacitance discharging into the Port 0 and Port 2 pins

when these pins make 1 to 0 transitions during bus

operations. In the worst cases (capacitive loading 100

pF), the noise pulse on the ALE line may exceed 0.45 V

with maxi VOL peak 0.6 V. A Schmitt Trigger use is not

necessary.

Note 3 : Typicals are based on a limited number of

samples and are not guaranteed. the values listed are at

room temperature and 5V.

Note 4 : Under steady state (non–transient)) conditions,

IOL must be externally limited as follows :

Maximum IOL per port pin :

10 mA

Maximum IOL per 8–bit port :

Port 0 :

26 mA

Ports 1, 2 and 3 : 15 mA

Maximum total IOL for all output pins : 71 mA

If IOL exceed the test condition, VOL may exceed the

related specification. Pins are not guaranteed to sink

current greater than the listed test conditions.

Figure 7. ICC Test Condition, Idle Mode.

All other pins are disconnected.

Figure 8. ICC Test Condition, Active Mode.

All other pins are disconnected.

Figure 9. ICC Test Condition, Power Down Mode.

Figure 10. Clock Signal Waveform for ICC Tests in Active and Idle Modes.

All other pins are disconnected.

TCLCH = TCHCL = 5 ns.

MATRA MHS

13

Rev. E (14 Jan.97)

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