TS68C429AMF1B_C 查看數據表（PDF） - Atmel Corporation
零件编号
产品描述 (功能)
生产厂家
TS68C429AMF1B_C Datasheet PDF : 43 Pages
| |||
Figure 7. Interrupt Cycle (IEIxx = 1)
TS68C429A
Notes: 1. If UDS = 1, D15-D8 stay hi-z else D15-D8 drive the bus with a stable unknown value.
2. If IEOxx goes low, neither vector nor DTACK are generated, else IEOxx stays inactive and a vector is generated (D7-D0 and
DTACK).
Table 8. Timing Characteristic
Number
Symbol
Parameter
Min
1
tAVCSL
Address valid to CS low
0
2
tRWVCSL
R/W valid to CS low
0
3
tDIVDSL
Data in valid to LDS/UDS low
0
4
tSVCL
CS, LDS/UDS, IACKxx valid to CLK-SYS low
5
5
tCLDKL
CLK-SYS low to DTACK low
-
6
tCLDOV
CLK-SYS low to data out valid
-
7
tDKLDOV
DTACK low to data out valid
-
8
tSHDKH
CS or LDS/UDS or IACKxx high to DTACK high
-
9
tSHDXZ
CS or LDS/UDS or IACKxx high to DTACK hi-z
-
10
tSHDOZ
CS or LDS/UDS or IACKxx high to data out hi-z
-
11
tILIOL
IEIxx or IACKxx low to IEOxx low
-
12
tIKHIOH
IACKxx high to IEOxx high
-
13
tIILDKL
IEIxx low to DTACK low
-
14
tIILDOV
IEIxx low to data out valid
-
15
tSH
CS, IACKxx, LDS/UDS inactive time
15
16
tDKLSH
DTACK low to CS or LDS/UDS or IACKxx high
0
17
tSHAH
CS or LDS/UDS high to address hold time
0
Max
T/G(1)
Unit
-
T
ns
-
T
ns
-
T
ns
-
T
ns
45
T
ns
50
T
ns
10
G
ns
35
G
ns
50
G
ns
25
G
ns
35
T
ns
40
T
ns
40
T
ns
45
T
ns
-
T
ns
-
G
ns
-
G
ns
13
2120A–HIREL–08/02
Share Link: 