TSL2562 查看數據表（PDF） - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS
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TSL2562 Datasheet PDF : 42 Pages
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TSL2562, TSL2563
LOW-VOLTAGE
LIGHT-TO-DIGITAL CONVERTER
TAOS066N − AUGUST 2010
Timing Register (1h)
The TIMING register controls both the integration time and the gain of the ADC channels. A common set of
control bits is provided that controls both ADC channels. The TIMING register defaults to 02h at power on.
Table 5. Timing Register
7
6
5
4
3
2
1
0
1h
Resv
Resv
Resv
GAIN
Manual
Resv
INTEG
TIMING
Reset Value:
0
FIELD
BIT
Resv
7−5
GAIN
4
Manual
3
Resv
2
INTEG
1:0
0
0
0
0
0
1
0
DESCRIPTION
Reserved. Write as 0.
Switches gain between low gain and high gain modes. Writing a 0 selects low gain (1×); writing a 1 selects
high gain (16×).
Manual timing control. Writing a 1 begins an integration cycle. Writing a 0 stops an integration cycle.
NOTE: This field only has meaning when INTEG = 11. It is ignored at all other times.
Reserved. Write as 0.
Integrate time. This field selects the integration time for each conversion.
Integration time is dependent on the INTEG FIELD VALUE and the internal clock frequency. Nominal integration
times and respective scaling between integration times scale proportionally as shown in Table 6. See Note 5
and Note 6 on page 5 for detailed information regarding how the scale values were obtained; see page 22 for
further information on how to calculate lux.
Table 6. Integration Time
INTEG FIELD VALUE
00
01
10
11
SCALE
0.034
0.252
1
−−
NOMINAL INTEGRATION TIME
13.7 ms
101 ms
402 ms
N/A
The manual timing control feature is used to manually start and stop the integration time period. If a particular
integration time period is required that is not listed in Table 6, then this feature can be used. For example, the
manual timing control can be used to synchronize the TSL256x device with an external light source (e.g. LED).
A start command to begin integration can be initiated by writing a 1 to this bit field. Correspondingly, the
integration can be stopped by simply writing a 0 to the same bit field.
Interrupt Threshold Register (2h − 5h)
The interrupt threshold registers store the values to be used as the high and low trigger points for the comparison
function for interrupt generation. If the value generated by channel 0 crosses below or is equal to the low
threshold specified, an interrupt is asserted on the interrupt pin. If the value generated by channel 0 crosses
above the high threshold specified, an interrupt is asserted on the interrupt pin. Registers THRESHLOWLOW
and THRESHLOWHIGH provide the low byte and high byte, respectively, of the lower interrupt threshold.
Registers THRESHHIGHLOW and THRESHHIGHHIGH provide the low and high bytes, respectively, of the
upper interrupt threshold. The high and low bytes from each set of registers are combined to form a 16-bit
threshold value. The interrupt threshold registers default to 00h on power up.
The LUMENOLOGY r Company
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www.taosinc.com
Copyright E 2010, TAOS Inc.
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