UPA1802 查看數據表（PDF） - NEC => Renesas Technology

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UPA1802

N-CHANNEL MOS FIELD EFFECT TRANSISTOR FOR SWITCHING

NEC => Renesas Technology 

ELECTRICAL CHARACTERISTICS (TA = 25 °C)

CHARACTERISTICS

SYMBOL

TEST CONDITIONS

Zero Gate Voltage Drain Current

IDSS

VDS = 20 V, VGS = 0 V

Gate Leakage Current

IGSS

VGS = ±12 V, VDS = 0 V

Gate Cut-off Voltage

• Forward Transfer Admittance

• Drain to Source On-state Resistance

VGS(off)

| yfs |

RDS(on)1

VDS = 10 V, ID = 1 mA

VDS = 10 V, ID = 3.5 A

VGS = 4.5 V, ID = 3.5 A

RDS(on)2 VGS = 4.0V, ID = 3.5 A

RDS(on)3 VGS = 2.5 V, ID = 3.5 A

Input Capacitance

Ciss

VDS = 10 V

Output Capacitance

Coss

VGS = 0 V

Reverse Transfer Capacitance

Crss

f = 1 MHz

Turn-on Delay Time

td(on)

VDD = 10 V

Rise Time

tr

ID = 3.5 A

Turn-off Delay Time

td(off)

VGS(on) = 4.0 V

Fall Time

tf

RG = 10 Ω

Total Gate Charge

QG

VDS = 16 V

Gate to Source Charge

QGS ID = 7.0 A

Gate to Drain Charge

QGD

VGS = 4.0 V

Diode Forward Voltage

VF(S-D) IF = 7.0 A, VGS = 0 V

µ PA1802

MIN. TYP. MAX. UNIT

10 µA

±10 µA

0.5 0.8 1.5 V

5

16

S

16 23 mΩ

17 25 mΩ

21 32 mΩ

970

pF

510

pF

230

pF

60

ns

210

ns

590

ns

820

ns

13

nC

3

nC

5

nC

0.74

V

TEST CIRCUIT 1 SWITCHING TIME

D.U.T.

RG

PG.

VGS

0

τ

τ = 1µs

Duty Cycle ≤ 1 %

RL

VGS

VGS

Wave Form

10 %

0

VGS(on) 90 %

VDD

ID

90 %

ID

ID

0 10 %

Wave Form

90 %

10 %

td(on) tr td(off) tf

ton

toff

TEST CIRCUIT 2 GATE CHARGE

D.U.T.

IG = 2 mA

RL

PG.

50 Ω

VDD

2

Data Sheet D12966EJ1V0DS00

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