UPD16434G-001-12 查看數據表（PDF） - NEC => Renesas Technology

零件编号

产品描述 (功能)

生产厂家

UPD16434G-001-12

1/8/ 1/15 DUTY LCD CONTROLLER/DRIVER

NEC => Renesas Technology 

µ PD16434

3. DATA INPUT/OUTPUT OPERATION

In the µ PD16434, a command/data consists of 1 byte (8 bits), and processing is performed each time a byte of

data is transferred in either the serial or parallel mode.

The end of a byte data transfer is confirmed by the byte counter (octal/binary counter) which counts eight /SCK

counts or two /STB counts.

This counter is unconditionally cleared, when /CS = high or RESET = high, and becomes ready to count a new byte

or data. Therefore, if /CS is set to high or RESET is input in the middle of a byte transfer, the byte transfer is not

guaranteed.

In the serial interface mode, data is treated as 8-bit serial data. It is regarded that 1 byte of data has been input or

output, when eight serial clock pulses (/SCK) are counted in the chip selected condition, then internal processing is

started. At the 8th rising edge of the /SCK, the µ PD16434 sets the /BUSY signal to low to inform the CPU that the

µ PD16434 is in a busy state.

When the internal processing completes, the µ PD16434 sets the /BUSY signal to high to inform the CPU that the

µ PD16434 is ready for the next byte transfer.

The serial data is input/output with the MSB first (refer to Figure 3–1 and Figure 3–2).

If the chip address selection function is specified in the serial interface mode, the 8-bit serial data (only the lower 2

bits have a meaning) for chip address information must be written first after the /CS falling edge. Only the chip, whose

address coincides with this information, can enter command input or data input/output operation (refer to Figure 3–3 and

Figure 3–4).

In the parallel interface mode, since the data bus (D3 to D0) is a 4-bit bus, data is treated as 4-bit × 2 parallel data.

When the parallel data strobe signal (/STB) is counted twice in the chip selected state, it is regarded that a byte of data

has been input/output, then the µ PD16434 enters the internal processing.

At the 2nd rising edge of the /STB, the µ PD16434 sets the /BUSY signal to low, to inform the CPU that the

µ PD16434 is in a busy state. When the internal processing completes, the µ PD16434 sets the /BUSY signal to high, to

inform the CPU that the µ PD16434 is ready for the next byte transfer.

In both input and output operation, the upper 4 bits of parallel data correspond to the first /STB, and the lower 4 bits

of parallel data correspond to the second /STB.

The parallel interface of the µ PD16434 is compatible with the µ PD82C43 I/O expander, so that the parallel data

can be input to the µ PD16434 in the same manner as sending 4-bit data twice to the µ PD82C43. In addition, 8-bit data

can be read out from the serial/parallel register of the µ PD16434 in the same way as reading 4-bit data twice from the

µ PD82C43.

The chip address selection function is always specified in the parallel interface mode. After the /CS falling edge, the

data on the D1 and D0 lines, read at the first falling edge of the /STB, becomes the chip address information. The lower 2

bits of the command code, output from the CPU as the data for selecting port 4 to port 7 of the µ PD82C43, are used as

the chip address information. After the /CS falling edge, the command code, output from the CPU at the second and

successive falling edges of the /STB, has no meaning for the µ PD16434 (refer to Figure 3–5 and Figure 3–6). Refer to 4.

SELECTING µ PD16434 INTERFACE FUNCTION WITH CPU for details on chip address function

selection.

Data Sheet S10299EJ4V0DS00

21

Share Link: