UPD16716 查看數據表（PDF） - NEC => Renesas Technology
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UPD16716 Datasheet PDF : 20 Pages
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µ PD16716
Timing Requirement (TA = –10 to +75°C, VDD1 = 2.5 to 3.6 V, VSS1 = 0 V, tr = tf = 5.0 ns)
Parameter
Clock Pulse Width
Clock Pulse High Period
Clock Pulse Low Period
Data Setup Time
Data Hold Time
Start Pulse Setup Time
Start Pulse Hold Time
POL21, POL22 Setup Time
POL21, POL22 Hold Time
STB Pulse Width
Last Data Timing
CLK-STB Time
STB-CLK Time
Time between STB and Start Pulse
POL-STB Time
STB-POL Time
Symbol
PWCLK
PWCLK(H)
PWCLK(L)
tSETUP1
tHOLD1
tSETUP2
tHOLD2
tSETUP3
tHOLD3
PWSTB
tLDT
tCLK-STB
tSTB-CLK
tSTB-STH
tPOL-STB
tSTB-POL
Condition
VDD1 = 3.3 V ± 0.3 V
VDD1 = 2.5 to 3.0 V
CLK ↑ → STB ↑
STB ↑ → CLK ↑
STB ↑ → STHR (STHL) ↑
POL ↑ or ↓ → STB ↑
STB ↓ → POL ↓ or ↑
MIN.
14
22
4
4
2
2
2
2
2
2
1.5
2
4
4
2
–5
4
TYP.
MAX.
Remark Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
CLK
ns
ns
CLK
ns
ns
14
Data Sheet S14417EJ1V1DS
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