UPD16879 查看數據表（PDF） - NEC => Renesas Technology
零件编号
产品描述 (功能)
生产厂家
UPD16879 Datasheet PDF : 32 Pages
| |||
µPD16879
VD
VD
LATCH
Fig 1. Delay Time of Serial Data
t(VD-LATCH)
104 clocks (8 bits × 13 bytes)
SCLK
t(SCLK-LATCH)
Ignored because LATCH is at low level
LATCH
50%
SDATA
D1 D2
D3
50%
50%
SCLK
t(SCLK-LATCH)
Ignored because LATCH is at low level
t(SCLK-LATCH)
tsetup thold
Table 1. Chopping Frequency (3rd byte D5 to D0 bit data, fCLK = 4.5 MHz) Typical Value
Input data
D5 to D0 bit
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
Chopping frequency
(kHz)
35.71
40.18
45.00
50.00
53.57
59.21
62.50
68.18
72.58
77.59
80.36
86.54
90.00
93.75
97.83
102.27
107.14
112.50
118.42
118.42
125.00
Input data
D5 to D0 bit
011101
011110
011111
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
Chopping frequency
(kHz)
132.35
132.35
140.63
140.63
150.00
150.00
160.71
160.71
160.71
173.08
173.08
173.08
187.50
187.50
187.50
204.55
204.55
204.55
204.55
225.00
Note When data are less than 7 (000111), PWM chopping doesn’t do it, and output pulse doesn’t occur.
When data are beyond 49, PWM chopping frequency becomes a 225 kHz fixation.
4
Data Sheet S14188EJ1V0DS00
Share Link: 