µPD17072,17073
Pin No.
Symbol
QFP TQFP
23
26 VDD
27
24
28
XOUT
25
29 XIN
26
30 REG1
Function
Output format
Positive power supply.
Supply 1.8 to 3.6 V (TA = –20 to +70 °C) to operate
all functions.
Do not apply voltage higher than that of VDD pin to
any pin other than VDD.
Pins for connecting crystal resonator for system
clock oscillation.
Output of voltage regulator for oscillation circuit.
Connect this pin to GND via 0.1-µF capacitor.
—
CMOS push-pull
—
—
At power-ON
reset
—
—
—
REG1
0.1 µF
27
31 REGLCD0
• REGLCD1, REGLCD0
—
28
32 CAPLCD0
29
33 CAPLCD1
LCD drive power pins.
• CAPLCD1, CAPLCD0
30
34 REGLCD1
Connect capacitors for doubler circuit to generate
LCD drive voltage, across these pins.
To configure doubler circuit, connect capacitors
as shown below.
REGLCD1
C1 = C2 = 0.1 µF
C3 = 0.01 µF
C1
CAPLCD1
C3
CAPLCD0
REGLCD0
C2
Caution The value of the LCD drive voltage differs
if the values of C1, C2, and C3 are changed
because of the configuration of the doubler
circuit.
—
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