µPD43256B
Write Cycle Timing Chart 2 (/CS Controlled)
Address (Input)
/CS (Input)
/WE (Input)
tWC
tAS
tCW
tAW
tWP
tWR
I/O (Input)
High impedance
tDW
Data in
tDH
High
impedance
Cautions 1. /CS or /WE should be fixed to high level during address transition.
•
2. When I/O pins are in the output state, therefore the input signals must not be applied to
the output.
Remark Write operation is done during the overlap time of a low level /CS and a low level /WE.
Data Sheet M10770EJCV0DS00
15