UPD4701AC 查看數據表（PDF） - NEC => Renesas Technology

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UPD4701AC

INCREMENTAL ENCODER COUNTER

NEC => Renesas Technology 

µPD4701A

PIN FUNCTIONS

CPU

interface

block

Mouse

interface

block

Pin Name

CS

X/Y

U/L

RESET X

RESET Y

D0 to 7

CF

SF

XA, XB

YA, YB

RIGHT

LEFT

MIDDLE

Input/Output

Input

Input

Input

Input

Output

(3-state)

Output

Output

Input

(Schmitt input)

Input

(Schmitt input)

Input

(Schmitt input)

Function

Chip Select input. “L” input activates outputs D0 to 7.

“H” input sets outputs D0 to 7 to high impedance.

Output data is latched on the fall edge of CS. “L” must be maintained during a

count data read.

Counter Select input. “L” input selects the X counter, and “H” input selects the

Y counter.

Byte Select input. “L” input selects the lower byte and “H” input selects the

upper byte, controlling data output.

Counter reset inputs. RESET X input resets the X counter, and RESET Y input

resets the Y counter. Both are active-“H”.

Bus for data output to the CPU. Outputs the byte data selected by the X/Y and

U/L inputs.

The data latched on the fall of CS is output.

Counter flag output. Set (= “L” output) when the X or Y counter changes while

CS = “H”. Reset (= “H” output) on the fall of CS. While CS = “L”, count flag

output is disabled and the “H” level is output.

Switch flag output. Becomes active (= “L” output) when the RIGHT, LEFT or

MIDDLE switch input is “L”.

X counter 2-phase signal input pins

Y counter 2-phase signal input pins

Key switch input pins. Key switch input are read as the high-order 4 bits of the

X counter and Y counter upper byte as the internal status.

Upper Byte

SF L R

M C11 C10 C9 C8

Key Input Status

Count Data

Power

VDD

supply

block

VSS

+5 V power supply connection pin

Ground pin

3

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