µPD72001-11, 72001-A8
AC Characteristics (TA = –40 to +85 °C, VDD = 3.3 V ± 0.3 V)
System interface:
Parameter
Symbol
Condition
Clock cycle
tCYK
TA = –10 to +70 °C
TA = –40 to +85 °C
Clock high-pulse width
tWKH
Clock low-pulse width
tWKL
Clock rise time
tKR
1.5 V → 2.2 V
Clock fall time
tKF
2.2 V → 1.5 V
Address setup time (vs. RD ↓)
tSAR
TA = –10 to +70 °C
TA = –40 to +85 °C
Address hold time (vs. RD ↑)
tHRA
TA = –10 to +70 °C
TA = –40 to +85 °C
RD pulse width
tWRL
TA = –10 to +70 °C
TA = –40 to +85 °C
Address → data output delay time
tDAD
TA = –10 to +70 °C
TA = –40 to +85 °C
RD → data output delay time
tDRD
TA = –10 to +70 °C
TA = –40 to +85 °C
RD → data float delay time
tFRD
Address setup time (vs. WR ↓)
tSAW
Address hold time (vs. WR ↑)
tHWA
TA = –10 to +70 °C
TA = –40 to +85 °C
WR pulse width
tWWL
TA = –10 to +70 °C
TA = –40 to +85 °C
Data setup time (vs. WR ↑)
tSDW
TA = –10 to +70 °C
TA = –40 to +85 °C
Data hold time (vs. WR ↑)
tHWD
TA = –10 to +70 °C
TA = –40 to +85 °C
Recovery time between RD and WR
tRV
TA = –10 to +70 °C
TA = –40 to +85 °C
Rated Value
Unit
MIN. MAX.
125 2000
ns
140 2000
ns
50
1000
ns
50
1000
ns
10
ns
10
ns
0
ns
5
0
ns
5
150
ns
155
120
ns
125
120
ns
125
10
120
ns
0
ns
0
ns
5
150
ns
155
120
ns
125
0
ns
5
180
ns
190
21