UPD75036GC 查看數據表（PDF） - NEC => Renesas Technology

零件编号

产品描述 (功能)

生产厂家

UPD75036GC

4 BIT SINGLE-CHIP MICROCOMPUTER

NEC => Renesas Technology 

µPD75036

4. ARCHITECTURE AND MEMORY MAP OF THE µPD75036

The µPD75036 has two architectural features:

• Bank configuration of data memory : Static RAM (1024 words × 4 bits)

Peripheral hardware (128 × 4 bits)

• Memory mapped I/O

Fig. 4-1 and 4-2 show the memory maps for the µPD75036.

Address

76

0000H MBE 0

0002H MBE 0

0004H MBE 0

0006H MBE 0

0008H MBE 0

000AH MBE 0

000CH MBE 0

Fig. 4-1 Program Memory Map

5

0

0 Internal reset start address (high-order 6 bits)

Internal reset start address (low-order 8 bits)

0 INTBT/INT4 start address (high-order 6 bits)

INTBT/INT4 start address (low-order 8 bits)

0 INT0 start address

(high-order 6 bits)

INT0 start address

(low-order 8 bits)

0 INT1 start address

(high-order 6 bits)

INT1 start address

(low-order 8 bits)

0 INTCSI start address

(high-order 6 bits)

INTCSI start address

(low-order 8 bits)

0 INTT0 start address

INTT0 start address

0 INTMFT start address

INTMFT start address

(high-order 6 bits)

(low-order 8 bits)

(high-order 6 bits)

(low-order 8 bits)

CALLF

!faddr

instruc-

tion

entry

address

BRCB

!caddr

instruc-

tion

branch

address

0020H

007FH

0080H

GETI instruction reference table

CALL !addr

instruction

subroutine

entry address

BR !addr

instruction

branch

address

BR $addr

instruction

relative

branch

address

(-15 to -1,

+2 to +16)

Branch

address and

subroutine

entry

address

specified in

GETI

instruction

07FFH

0800H

0FFFH

1000H

1FFFH

2000H

2FFFH

3000H

3F7FH

BRCB !caddr instruc-

tion branch address

BRCB !caddr instruc-

tion branch address

BRCB !caddr instruc-

tion branch address

Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address

with only the low-order 8 bits of the PC changed.

15

Share Link: