UPD75048CW 查看數據表（PDF） - NEC => Renesas Technology
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UPD75048CW Datasheet PDF : 68 Pages
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µPD75048
SERIAL TRANSFER OPERATION
Two-Line and Three-Line Serial I/O Modes (SCK: internal clock output)
Parameter
SCK Cycle Time
SCK High-, Low-Level
Widths
SI Set-Up Time (vs. SCK ↑)
SI Hold Time (vs. SCK ↑ )
SCK ↓→ SO Output
Delay Time
Symbol
Conditions
MIN.
tKCY1
VDD = 4.5 to 6.0 V
1600
3800
tKL1
VDD = 4.5 to 6.0 V
tKCY1/2-50
tKH1
tKCY1/2-150
tSIK1
150
tKSI1
400
tKSO1
RL = 1kΩ, CL = 100pF* VDD = 4.5 to 6.0V
TYP.
MAX.
250
1000
Unit
ns
ns
ns
ns
ns
ns
ns
ns
TWO-LINE AND THREE-LINE SERIAL I/O MODES (SCK: external clock input)
Parameter
SCK Cycle Time
SCK High-, Low-Level
Widths
SI Set-Up Time (vs. SCK ↑)
SI Hold Time (vs. SCK ↑)
SCK ↓→ SO Output
Delay Time
Symbol
Conditions
MIN.
tKCY2
VDD = 4.5 to 6.0V
800
3200
tKL2
VDD = 4.5 to 6.0V
400
tKH2
1600
tSIK2
100
tKSI2
400
tKSO2
RL = 1kΩ, CL = 100 pF* VDD = 4.5 to 6.0V
TYP.
*: RL and CL are load resistance and load capacitance of the SO output line.
MAX.
300
1000
Unit
ns
ns
ns
ns
ns
ns
ns
ns
51
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