UPD75208CW 查看數據表（PDF） - NEC => Renesas Technology
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UPD75208CW Datasheet PDF : 62 Pages
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µPD75208
4. ARCHITECTURE AND MEMORY MAP OF THE µPD75208
The µPD75208 has three architectural features:
• Bank configuration of data memory : Static RAM (448 words × 4 bits)
Display data memory (49 words × 4 bits)
Peripheral hardware (128 × 4 bits)
• Bank configuration of general registers: 8 × 4 banks (for operation in 4-bit units)
4 × 4 banks (for operation in 8-bit units)
• Memory mapped I/O
Fig. 4-1 and 4-2 show the memory maps for the µPD75208.
Address
765
0000H MBE RBE 0
0002H MBE RBE 0
0004H MBE RBE 0
0006H MBE RBE 0
0008H MBE RBE 0
000AH MBE RBE 0
000CH MBE RBE 0
000EH MBE RBE 0
Fig. 4-1 Program Memory Map
Internal Reset Start Address
Internal Reset Start Address
INTBT/INT4 Start Address
INTBT/INT4 Start Address
INT0 Start Address
INT0 Start Address
INT1 Start Address
INT1 Start Address
INTSIO Start Address
INTSIO Start Address
INTT0 Start Address
INTT0 Start Address
NTTPG Start Address
INTTPG Start Address
INTKS Start Address
INTKS Start Address
0
(High-Order 5 Bits)
(Low-Order 8 Bits)
(High-Order 5 Bits)
(Low-Order 8 Bits)
(High-Order 5 Bits)
(Low-Order 8 Bits)
(High-Order 5 Bits)
(Low-Order 8 Bits)
(High-Order 5 Bits)
(Low-Order 8 Bits)
(High-Order 5 Bits)
(Low-Order 8 Bits)
(High-Order 5 Bits)
(Low-Order 8 Bits)
(High-Order 5 Bits)
(Low-Order 8 Bits)
CALLF
! faddr
Instruction
Entry
Address
BRCB
! caddr
Instruction
Branch
Address
CALL ! addr
Instruction
Subroutine Entry
Address
BR ! addr
Instruction Branch
Address
0020H
007FH
0080H
07FFH
0800H
0FFFH
1000H
1F7FH
GETI Instruction Reference Table
BR $addr
Instruction
Relative Branch
Address
(–15 to –1,
+2 to +16) Branch Destination
Address Specified
by GETI Instruction,
Subroutine Entry
Address
BRCB
! caddr Instruction
Branch Address
Remarks In all cases other than those listed above, branch to the address with only the lower 8 bits of the PC
changed is enabled by BR PCDE and BR PCXA instructions.
12
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