UPD75238GJ 查看數據表（PDF） - NEC => Renesas Technology
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UPD75238GJ Datasheet PDF : 190 Pages
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µPD75238
APPENDIX A µPD75238 SERIES PRODUCT FUNCTION LIST
Item
Product
µPD75217
µPD75236
µPD75237
µPD75238
µPD75P238
ROM
RAM
Instruction
cycle
When main
system clock
is selected
24448 × 8
16256 × 8
768 × 4
0.95 µs/1.91 µs/
15.3 µs
(at 4.19 MHz)
0.95 µs/1.91 µs/
3.82 µs/15.3 µs
(at 4.19 MHz)
24448 × 8
32640 × 8
1024 × 4
0.67 µs/1.33 µs/2.67 µs/10.7 µs (at 6.0 MHz)
When sub-
system clock
is selected
I/O lines
(including FIP
dual-function
pins and
excluding
FIP-exclusive
pins)
Total number
of I/O lines
Number of
input lines
Number of I/O
lines
33
8
20: Eight lines
for driving
LED
122 µs (at 32.768 kHz)
64
16
24: 12 lines for driving LED
Number of
output lines
A/D converter
FIP control-
ler/driver
High-voltage
output
Number of
segments
5
None
26: 40 V (max.)
9 to 16
24
8 : 8-bit resolution
34: 40 V (max.)
9 to 24
Number of
digits
Timer
Serial interface
Four channels
One channel:
3-wire system
9 to 16
Five channels
Two channels
SBI/3-wire system
3-wire system
Number of interrupt sources
10
Range of operating temperature
Operating power voltage
Package
64-pin plastic
shrink DIP
64-pin plastic
QFP
11
-40 to +85 °C
2.7 to 6.0 V
94-pin plastic QFP
-40 to +70 °C
5
94-pin plastic
QFP
94-pin ceramic
LCC with a
window
185
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