UPD77017GC-XXX-9EU 查看數據表（PDF） - NEC => Renesas Technology

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UPD77017GC-XXX-9EU

16 bits, Fixed-point Digital Signal Processor

NEC => Renesas Technology 

µPD77015, 77017, 77018

(2) General register used as 32 bits register

Bit 31 to bit 0 of general register are treated as 32 bits register, when it is used for a operand of exponent

instruction.

(3) General register used as 24 bits register

Bit 39 to bit 16 of general register are treated as 24 bits register, when it is used for destination with extended

sign for a load/store instruction.

(4) General register used as 16 bits register

Bit 31 to bit 16 of general register are treated as 16 bits register, when it is used for the following aims.

(a) Signed operand for multiplier

(b) Source/destination for load/store instruction

Bit 15 to bit 0 of general register are treated as 16 bits register, when it is used for the following aims.

(c) Unsigned operand for multiplier

(d) Shift value for shift instruction

(e) Source/destination for load/store instruction

(f) Source/destination for inter-register transfer instruction

(g) Destination for immediate data set instruction

(f) Hardware loop times

(5) General register used as 8 bits register

Bit 39 to bit 32 of general register are treated as 8 bits register, when it is used for source/destination of load/

store instruction.

2.3.2 MAC: Multiply ACcumulator

MAC multiplies a pair of 16 bits data, and adds or subtract the result and 40 bits data. MAC outputs 40 bits

data.

MAC operates three types of multiplication: signed data × signed data, signed data × unsigned data and

unsigned data × unsigned data.

Result of multiplication and 40 bits data for addition can be added after 1 or 16 bits arithmetic shift right.

2.3.3 ALU: Arithmetic Logic Unit

ALU performs arithmetic operation and logic operation. Both input/output data are 40 bits.

2.3.4 BSFT: Barrel ShiFTer

BSFT performs shift right/left operation. Both input/output data are 40 bits. There are two types of shift right

operations; arithmetic shift right which sign is extended, and logic shift right which is input 0 in MSB first.

2.3.5 SAC: Shifter And Count Circuit

SAC calculates and outputs shift value for normalization. SAC is input 32 bits data and outputs the 40 bits

data. Then, bit 39 to bit 5 of output data is always 0.

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