HSP50016-EV 查看數據表（PDF） - Intersil

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HSP50016-EV

DDC Evaluation Platform

Intersil 

HSP50016-EV

Up Loading Data via PC's Parallel Port

Data is up loaded to the host PC through the “Select” serial

status line of the PC's parallel port. The PC up loads data by

monitoring the state of the PCRD1 serial output line on the

HSP50016-EV's Parallel Port Bus. The mapping of the

evaluation board signals to the PC’s parallel port is given in

Table 5.

DDC Data and Control via P1 Connector

When it is desired to use P1 connector for data input, the

registers driving the data bus are three-stated by removing

the jumper JP5 (see Configuration Jumper Field Section).

The DIN0-15 pins on P1 are then used to drive the input

pins of the HSP50016. If all 16 pins are not used, then the

DIN bus should be loaded starting from bit 15 down. When

JP5 is not installed, all data input pins must either be

driven by an external data source or grounded to avoid

damage to the board.

To control the DDC from the P1 or P2 connector, the PCD0-

7 bus is exercised via the connector. In this case, the user

must operate this bus in the same manner as the PC

exercises it from the parallel port as described above. No

jumper selection is necessary in this case; it is only

necessary to leave the parallel port connector J1

unconnected.

To operate the Test Access Port from P2, the shorting

jumper on JP18 is removed. The TAP pins are then

controlled directly from P2 according to the TAP

Specification. In this case, the SEL0-2 lines should be set to

0, 0, and 1 respectively.

DDC Clocking Modes

The HSP50016-EV provides the DDC with one of three

jumper selectable clock sources. The three clock choices

consist of an on-board oscillator, a user provided external

clock, and a clock generated by toggling the LSB of the

Control Register U16. The clock source is select by placing a

jumper on either JP1, 2 or 3. To support applications in

which multiple evaluation boards are daisy chained together,

a clock output line is routed to the HSP50016-EV's output

connector P2.

An external clock may be selected by inserting a jumper on

the header JP1. In this mode, an external clock supplied to

the CLKIN pin of the 96 pin Input Connector is provided to

the DDC. This configuration supports the use of a common

clock between daisy-chained evaluation boards by wiring

CLKOUT from the P2 Output Connector of one board to the

CLKIN pin of another board's P1 Input Connector. Since

there is no synchronization between the externally provided

clock and data transfers to the HSP50016-EV's I/O

Registers, the PC would typically provide the DDC with

asynchronous control in this mode.

The on-board oscillator is selected as a clock source by JP2.

In this mode, the oscillator on board the HSP50016-EV is

supplied as a clock to the DDC. Since data transfers to the

DDC via the HSP50016-EV’s I/O Registers are much slower

than the DDC’s data rate using the oscillator clock, the PC

can only be used to provide the DDC with asynchronous

control in this mode.

The LSB of the Control Register U16 is selected as the clock

source if a jumper is inserted in the header JP3. In this

mode, the clock signal is generated by using register writes

to toggle the PCCLK bit. Since the clock may be controlled

by software, input and control register writes and the output

shift register reads can be performed synchronously with the

clock. Consequently, the HSP50016-EV can be used as a

hardware modeler where input and output data vectors are

transferred via the PC's parallel port.

Configuration Jumper Field

The HSP50016-EV is configured for operation by placing

jumpers in the headers JP1-3 and JP5-18. As shown in

Table 1, the jumper field has areas dedicated for clock

selection, register output enables and board address

selection. The default jumper placement is shown in Figure 1

and Table 1. Each HSP50016-EV leaves the factory

jumpered with the default configuration.

The Clock Select jumpers are used to specify one of the

three available DDC clocking modes. These include

EXT_CLK for selection of an external clock source,

OSC_CLK for selection of the on board oscillator clock, and

PC_CLK for selection of a register driven clock using the

LSB of the CTL Control Register. The clocking modes are

described in the DDC Clocking Modes Section of this

manual. Note: Normally, only one clock source may be

selected at a time. In any mode, the input and output clocks

may be negated independently by removing the jumpers on

JP14 and JP15.

The output of the Input Registers U12 and U13 are enabled

by placing a jumper on JP5 (see Bus and Register Structure

Sections) If a jumper is removed, the output of the respective

register is three stated.

The Board Address Jumpers are used to specify the

HSP50016-EV board address used for data transfers via the

Parallel Port Bus. An address from 0 to 7 may be selected by

inserting a jumper in positions ADDR0 thru ADDR7

respectively. Only one jumper may be inserted in this field.

The jumper JP18 is used to select the source of data for the

IEEE 1149.1 Test Access Port (TAP) bus. Inserting this

jumper enables the PC to drive this bus, while removing it

enables control from the P1 connector.

JP19 selects whether the IQSTB line is pulled up or down.

Placing the jumper between header pins 1 and 2 pulls

IQSTB up, while shorting pins 2 and 3 pulls IQSTB down.

The position of the jumper is only meaningful when IQSTB is

12

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