VORTEX86SX 查看數據表（PDF） - Unspecified

零件编号

产品描述 (功能)

生产厂家

VORTEX86SX

32-BIT x86 Embedded SoC

Unspecified 

Vortex86SX

32-Bit x86 Embedded SoC

Ring Indicator. This active low input is for the UART ports. A handshake

signal notifies the UART that the telephone ring signal is detected by the

modem. The CPU can monitor the status of the RI_n signal by reading bit 6 of

the Modem Status Register (MSR). An RI_n signal states the change from low

G1

RI3/SIORDY

I

to high after the last MSR read sets bit 2 of the MSR to a “1”. If bit 3 of the

Interrupt Enable Register is set, the interrupt is generated when RI_n changes

state.

Note: Bit 6 of the MSR is the complement of RI_n.

IDE Secondary Channel IO Channel Ready.

Data Terminal Ready. This is an active low output for the UART port. A

handshake output signal signifies the modem that the UART is ready to

establish data communication link. This signal can be programmed by writing

F1

DTR3_/SDACK_

O

to bit 0 of Modem Control Register (MCR). The hardware reset will clear the

DTR_n signal to be inactive during the loop-mode operation.

IDE Secondary Channel DMA Acknowledge.

Request to Send. Active low Request to Send output for UART port.

A handshake output signal notifies the modem that the UART is ready to

transmit data. This signal can be programmed by writing to bit 1 of Modem

U6

RTS4_/SINT

I/O

Control Register (MCR). The hardware reset will clear the RTS_n signal to be

inactive mode (high). It is forced to be inactive during the loop-mode

operation.

IDE Secondary Channel Interrupt.

Ring Indicator. This active low input is for the UART ports. A handshake

signal notifies the UART that the telephone ring signal is detected by the

modem. The CPU can monitor the status of the RI_n signal by reading bit 6 of

the Modem Status Register (MSR). An RI_n signal states the change from low

V5

RI4/SA1

I/O

to high after the last MSR read sets bit 2 of the MSR to a “1”. If bit 3 of the

Interrupt Enable Register is set, the interrupt is generated when RI_n changes

state.

Note: Bit 6 of the MSR is the complement of RI_n.

IDE Secondary Channel Device Address.

Data Set Ready. This active low input is for the UART ports. A handshake

signal notifies the UART that the modem is ready to establish the

communication link. The CPU can monitor the status of the DSR_n signal by

reading bit5 of the Modem Status Register (MSR). A DSR_n signal states the

H1

DSR3_/SCBLID_

I

change from low to high after the last MSR read sets bit1 of the MSR to a “1”.

If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when

DSR_n changes state.

Note: Bit 5 of the MSR is the complement of DSR_n.

IDE Secondary Channel Cable Assembly Type Identifier.

Data Terminal Ready. This is an active low output for the UART port. A

handshake output signal signifies the modem that the UART is ready to

establish data communication link. This signal can be programmed by writing

V6

DTR4_/SA0

O

to bit 0 of Modem Control Register (MCR). The hardware reset will clear the

DTR_n signal to be inactive during the loop-mode operation.

IDE Secondary Channel Device Address.

Data Carrier Detect. This active low input is for the UART ports. A handshake

signal notifies the UART that the carrier signal is detected by the modem. The

CPU can monitor the status of the DCD_n signal by reading bit 7 of the

Modem Status Register (MSR). A DCD_n signal states the change from low to

R6

DCD4_/SA2

I

high after the last MSR read sets bit 3 of the MSR to a “1”. If bit 3 of the

Interrupt Enable Register is set, the interrupt is generated when DCDJ

changes state.

Note: Bit 7 of the MSR is the complement of DCD_n.

IDE Secondary Channel Device Address.

Vortex86SX Brief Datasheet

17

Version 1.001

Share Link: