VSC7217UC 查看數據表（PDF） - Vitesse Semiconductor

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VSC7217UC

Multi-Gigabit Interconnect Chip

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Mutli-Gigabit Interconnect Chip

Preliminary Datasheet

VSC7217

Figure 7: Receive Timing, RMODE(1:0) = 01

REFCLK

(DUAL = 0)

REFCLK

(DUAL = 1)

Rn(7:0)

IDLEn

KCHn

Valid

Valid

Valid

ERRn

Figure 8: Receive Timing, RMODE(1:0) = 1X

RCLKn

(DUAL = 0)

RCLKn

(DUAL = 1)

Rn(7:0)

IDLEn

KCHn

Valid

ERRn

Valid

Valid

The data coming from the decoder is clocked into the elastic buffer by the recovered clock from the chan-

nel’s CRU. The data is clocked out of the elastic buffers with word clock. If the transmitting device’s REFCLK

is not precisely frequency locked to a receive channel’s word clock, then the channel’s elastic buffer will tend to

gradually fill or empty as the recovered clock (which is by definition frequency locked to the transmitter’s

REFCLK) steadily drifts in phase relative to the word clock.

To accommodate frequency differences between a transmitter’s REFCLK and the word clock, the

VSC7217 can automatically perform rate matching by either deleting or duplicating IDLE characters. The

FLOCK input must be LOW to enable rate matching which, based on how the WSI input is connected, can

either be performed in each channel individually or can be performed in parallel across a group of channels that

are word-aligned. This is discussed in detail in the following section describing Word Alignment. The user

must ensure that the frequency at which IDLEs are simultaneously transmitted on each channel accommodates

the frequency differences, if any, in their system architecture. Not meeting the IDLE density requirements could

result in Underrun/Overrun Errors.

Page 10

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52325-0, Rev. 3.0

6/14/00

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