VSC7217 查看數據表（PDF） - Vitesse Semiconductor

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VSC7217

Multi-Gigabit Interconnect Chip

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

VSC7217

Multi-Gigabit Interconnect Chip

Figure 15: Transmit Input Timing Waveforms with TMODE = 11X (“ASIC-Friendly” Timing)

TBCn

(or TBCA)

Internal Clock

(from PLL)

Tn(7:0)

C/Dn

Valid

WSENn

TS

Valid

TS

Valid

Table 10: Transmit Input AC Characteristics with TMODE = 11X

Parameters

Description

Min

Max Units

Conditions

TS

Input Skew relative to the rising

edge of TBCn or TBCA

—

Measured between the valid data

2.0

bc level of the input and the 1.4V point

of TBCn or TBCA, bc = Bit Clock.

Figure 16: Transmit Serial Timing Waveforms

TXn+, TXn-

REFCLK

(or TBCn)

TSDR, TSDF

TX0

TLAT

Table 11: Transmit Serial AC Characteristics

Parameters

TSDR, TSDF

TLAT

TJ

TDJ

Description

TXn+/- Rise and Fall Times

Latency, REFCLK to TX0

Latency, TBCA to TX0

Latency, TBCB/C/D to TX0

Serial Data Output

Total Jitter (p-p)

Serial Data Output

Deterministic Jitter (p-p)

Min

—

22bc+0.2ns

36bc+0.0ns

32bc+0.1ns

—

—

Max

330

22bc+0.8ns

38bc+0.3ns

42bc+0.6ns

192

80

Units

ps

bc + ns

ps

ps

Conditions

Measured between 20% to

80% of the valid data level.

ENDEC=1 TMODE=000

ENDEC=1 TMODE=10X

ENDEC=1 TMODE=101

IEEE 802.3z Clause 38.69,

tested on a sample basis.

IEEE 802.3z Clause 38.69,

tested on a sample basis.

G52325-0, Rev. 3.0

6/14/00

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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