VSC7217 查看數據表（PDF） - Vitesse Semiconductor

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VSC7217

Multi-Gigabit Interconnect Chip

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Mutli-Gigabit Interconnect Chip

Preliminary Datasheet

VSC7217

mit data rate that is locked to the selected input timing source. This is an especially important when DUAL is

HIGH and input timing is referenced to REFCLK, since the falling edge is NOT used. The internal clock active

edges are placed coincident with the REFCLK rising edges and halfway between the REFCLK rising edges in

this mode.

A similar situation exists when TBCn is used to define a data eye. Only the rising edges of TBCn are used

to define the external data timing. The internal clock active edges are placed at 90° and 270° points between

consecutive TBCn rising edges (which are assumed to be 360° apart).

Figure 2: Transmit Timing, TMODE(2:0) = 000

REFCLK

(DUAL = 0)

REFCLK

(DUAL = 1)

Tn(7:0)

C/Dn

Valid

WSENn

Valid

Valid

TBCA

or

TBCn

Tn(7:0)

C/Dn

WSENn

Figure 3: Transmit Timing, TMODE(2:0) = 10X

Valid

Valid

Valid

Figure 4: Transmit Timing, TMODE(2:0) = 11X (“ASIC-Friendly” Timing

0o

90o

180o

270o

360o

TBCA or TBCn

Tn(7:0)

C/Dn

Valid

Valid

Valid

WSENn

Page 4

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52325-0, Rev. 3.0

6/14/00

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