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VSC834UB 查看數據表(PDF) - Vitesse Semiconductor

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VSC834UB Datasheet PDF : 16 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
2.5Gb/s 17x17 Crosspoint Switch
with Input Signal Activity (ISA) Monitoring
ADDR[5:0]
DATA[4:0]
CSB
WRB
RDB
CONFIG
Figure 4: Program Timing
TsCSB
TsWRB
ThWRB
TsCONFIG
Datasheet
VSC834
Table 4: Programing Port Interface Timing
Parameter
Description
Tconfig
TpdADDR
TpdRDB
Tpdint
Tpdstate
TsRDB
ThRDB
TsWRB
ThWRB
TsCONFIG
TsCSB
TpwCONFIG
TpwWRB
TpwRDB
TtsDATA
TsALE
Switch configuration delay
Data read propagation delay from ADDR
Data read propagation delay from RDB (1)
Interrupt propagation delay from MONCLK (2)
MONCLK to internal state register change delay (2)
ADDR to RDB setup time
RDB to ADDR hold time
WRB setup time (for either ADDR or DATA)
WRB hold time (for either ADDR or DATA)
WRB to CONFIG setup time
CSB setup time (to either WRB or RDB)
CONFIG pulse width (high)
WRB pulse width (low and high)
RDB pulse width (low and high)
DATA tri-state delay (from either RDB or CSB) (2)
ALE setup time (for multiplexed ADDR/DATA bus)
Note 1: Measured from falling edge.
Note 2: Measured from rising edge.
Min
Max
Units
-
6
ns
-
30
ns
-
7
ns
-
50
ns
-
6
ns
5
-
ns
3
-
ns
5
-
ns
3
-
ns
1
-
ns
0
-
ns
10
-
ns
10
-
ns
10
-
ns
-
10
ns
5
-
ns
Page 6
© VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52247-0, Rev 4.2
02/09/01

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