VSC8113QB 查看數據表（PDF） - Vitesse Semiconductor

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VSC8113QB

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

Data Sheet

VSC8113

Table 7: Receive Data Output Timing Table (STS-3 Operation)

Parameter

Description

Min

TRXCLKIN Receive clock period

-

TRXLSCKT Receive data output byte clock period

-

TRXVALID

Time data on RXOUT [7:0] and FP is valid before and

after the rising edge of RXLSCKOUT

22

TPW

Pulse width of frame detection pulse FP

-

Typ

6.43

51.44

-

51.44

Max

-

-

-

-

Units

ns

ns

ns

ns

TXCLKOUT-

TXCLKOUT+

TXDATAOUT+

TXDATAOUT-

Figure 11: Transmit High Speed Data Timing Diagram

TTXCLK

TSKEW TSKEW

Table 8: Transmit High Speed Data Timing Table (STS-12 Operation)

Parameter

Description

Min

TTXCLK

Transmit clock period

-

TSKEW

Skew between the falling edge of TXCLKOUT+ and

valid data on TXDATAOUT

-

Typ

1.608

-

Max

-

250

Units

ns

ps

Table 9: Transmit High Speed Data Timing Table (STS-3 Operation)

Parameter

TTXCLK

TSKEW

Description

Transmit clock period

Skew between the falling edge of TXCLKOUT+ and

valid data on TXDATAOUT

Min

Typ

Max

Units

-

6.43

-

ns

-

-

250

ps

Page 12

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52154-0, Rev 4.2

3/19/99

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