VSC8114 查看數據表（PDF） - Vitesse Semiconductor

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VSC8114

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery

Vitesse Semiconductor 

Data Sheet

VSC8114

VITESSE

SEMICONDUCTOR CORPORATION

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

Important note: The 11 ns max Tpd on the PM5355 assumes a 50pf load @ 60ps/pf, therefore 3 ns of the

max delay is due to loading. The VSC8114 input (TXLSCKIN) plus package is about 6pf. Assuming about 1 pf/

inch of 75 ohm trace on FR4 plus the VSC8114 6pf load, the user would in most cases choose option 1.

DC Coupling and Terminating High-speed PECL I/Os

The high speed signals on the VSC8114 (RXDATAIN, RXCLKIN, TXDATAOUT, REFCLKP, LOSPECL)

use 3.3/5V programmable PECL I/Os which can be direct coupled to either +3.3V PECL or +5V PECL signals

from the optics. These PECL levels are essentially ECL levels shifted positive by 3.3 volts or 5 volts. These

PECL I/Os are referenced to the VDDP supply (VDDP) and are terminated to ground. To program these I/Os for

either 3.3V or 5V interface, the 3 VDDP pins (pin 9, 15, 21) are required to connect to 3.3V or 5V supplies

accordingly.

AC Coupling and Terminating High-speed PECL I/Os

If the optics modules provide ECL level interface, the high speed signals can be AC coupled to the

VSC8114 as well. The PECL receiver inputs of the VSC8114 are internally biased at VDD/2. Therefore, AC-

coupling to the VSC8114 inputs is accomplished by providing the pull-down resistor for the open-source PECL

output and an AC-coupling capacitor used to eliminate the DC component of the output signal. This capacitor

allows the PECL receivers of the VSC8114 to self-bias via its internal resistor divider network (see Figure 14).

The PECL output drivers are capable of sourcing current but not sinking it. To establish a LOW output

level, a pull-down resistor, traditionally connected to VDD-2.0V, is needed when the output FET is turned off.

Since VDD-2.0V is usually not present in the system, the resistor should be terminated to ground for conve-

nience. The VSC8114 output drivers should be either AC-coupled to the 5.0V PECL inputs of the optics mod-

ule, or translated (DC level shift). Appropriate biasing techniques for setting the DC-level of these inputs should

be employed.

The dc biasing and 50 ohm termination requirements can easily be integrated together using a thevenin

equivalent circuit as shown in Figure 14. The figure shows the appropriate termination values when interfacing

3.3V PECL to 5.0V PECL. This network provides the equivalent 50 ohm termination for the high speed I/Os

and also provides the required dc biasing for the receivers of the optics module. Table 15 contains recommended

values for each of the components.

TTL Input Structure

The TTL inputs of the VSC8114 are 3.3V TTL which can accept 5.0V TTL levels within a given set of tol-

erances (see Table 8). The input structure, shown in Figure 14, uses a current limiter to avoid overdriving the

input FETs.

Initialization

The VSC8114 contains a “RESET” cap’s pin which is only needed for VLSI production test requirements

at Vitesse. The chip will initialize on its own as data is clocked through the device. The receive section will

frame align on the A1, A2 boundary of the incoming SONET/SDH data stream. (See Receive section on page

3).

G52185-0, Rev 4.0

11/1/99

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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