VSC8132QR 查看數據表（PDF） - Vitesse Semiconductor
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VSC8132QR Datasheet PDF : 14 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
2.488Gb/s 1:32 SONET/SDH Demux
Preliminary Data Sheet
VSC8132
Functional Description
High-Speed Clock and Data Interface
The incoming high-speed data and high-speed clock are received by high-speed inputs DI+ and CLKI+.
The inputs are internally biased to accommodate AC-coupling.
The data and clock inputs are internally terminated by a center-tapped resistor network. For differential
input DC-coupling, the network is terminated to the appropriate termination voltage, VTERM providing a 50Ω to
VTERM termination for both true and complement inputs. For differential input AC-coupling, the network is ter-
minated to VTERM via a blocking capacitor.
In most situations, these inputs will have high transition density and little DC offset. However, in cases
where this does not hold, direct DC connection is possible. All serial data and clock inputs have the same circuit
topology as shown in Figure 1. The reference voltage is created by a resistor divider as shown. If the input sig-
nal is driven differentially and DC-coupled to the part, the mid-point of the input signal swing should be cen-
tered about this reference voltage and not exceed the maximum allowable amplitude. For single-ended, DC-
coupling operations, it is recommended that the user provides an external reference voltage which has better
temperature and power supply noise rejection than the on-chip resistor divider. The external reference should
have a nominal value equivalent to the common mode switch point of the DC-coupled signal, and can be con-
nected to either side of the differential gate.
Figure 1: High-Speed Clock and Data Inputs
Chip Boundary
VCC = 3.3V
1.65V
CIN
3kΩ
Z0
100nF
VTERM
Z0
CAC
100nF
CIN
100nF
50Ω
3kΩ
II
50Ω
1.65V
3kΩ
3kΩ
VEE = 0V
Page 2
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52250-0, Rev 3.1
12/7/00
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