VSC8140TW 查看數據表（PDF） - Vitesse Semiconductor

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VSC8140TW

2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

Figure 2: Enabling FIFO Operation

PLL locked to reference clock.

RESET

Minimum 5 CLK16 cycles

FIFO Mode Operation

Transparent Mode Operation

Holding RESET “low” for a minimum of 5 CLK16 cycles, then setting “high” enables FIFO operation.

Holding RESET constantly “low” bypasses the FIFO for transparent mode operation.

Figure 3: DC Termination of Low-Speed LVPECL RXCLK16O, RXCLK16_32O, TXCLK16O Outputs

VSC8140

Split-end equivalent termination is ZO to VTERM VCC

R1 = 125Ω R2 = 83Ω, ZO=50Ω, VTERM= VCC-2V

R1

Zo

R1

downstream

Zo

R1||R2 = ZO

R2

R2

VCCR2 + VEER1

R1+R2

= VTERM

VEE

Figure 4: DC Termination of Low-Speed LVPECL RXCLK16O, RXCLK16_32O, TXCLK16O Outputs

VSC8140

Zo

downstream

R1 =50Ω

VCC-2V

R1 =50Ω

VCC-2V

G52251-0, Rev. 4.0

9/6/00

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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