VITESSE
SEMICONDUCTOR CORPORATION
2.488Gb/s SONET/SDH
STS-48/STM-16 Section Terminator
Advance Product Information
VSC8151
Figure 10: Transmit Frame Pulse Timing Diagram
Transmitted
Frame bytes
E2
E2
E2
Payload bytes of Row 9
TXFPOUT
TB
TFPW
Table 9: Transmit Frame Pulse Timing
Parameter
TFPW
TB (OC-48)
TB(OC-12)
TB(OC-3)
Description
Transmit Frame Pulse Width
Transmitted Byte Cycle Time
Transmitted Byte Cycle Time
Transmitted Byte Cycle Time
Min
Typ
Max
—
51.2
—
—
3.2
—
—
12.8
—
—
51.2
—
Figure 11: On Chip Register File Access Port Timing Diagram
TXADDR[5:0]
Units
ns
ns
ns
ns
TXOHDATA[7:0]
TXOHWI
TXWRENA
TSU
TWE
TH
TCYC
Table 10: On Chip Register File Access Port Timing
Parameter
TSU
TH
TWE
TCYC
Description
Setup time for data/address
Hold time for data/address
Write enable low
Write cycle time
Min
Typ
50
—
50
—
50
—
375
—
Max
—
—
—
—
Units
ns
ns
ns
ns
Page 16
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52225-0, Rev. 2.9
12/1/99