25Q32VFIG 查看數據表（PDF） - Winbond

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25Q32VFIG

32M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI

Winbond 

W25Q32V

10.1.6 Status Register Protect (SRP1, SRP0)

The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register

(S8 and S7). The SRP bits control the method of write protection: software protection, hardware

protection, power supply lock-down or one time programmable (OTP) protection.

SRP1 SRP0 /WP

Status

Register

Description

0

0

X

Software

Protection

/WP pin has no control. The Status register can be written to

after a Write Enable instruction, WEL=1. [Factory Default]

0

1

0

Hardware

Protected

When /WP pin is low the Status Register locked and can not

be written to.

0

1

1

Hardware When /WP pin is high the Status register is unlocked and can

Unprotected be written to after a Write Enable instruction, WEL=1.

1

0

X

Power Supply Status Register is protected and can not be written to again

Lock-Down(1) until the next power-down, power-up cycle.(2)

1

1

X

One Time

Program(1)

Status Register is permanently protected and can not be

written to.

Note:

1. These features are available upon special order. Please contact Winbond for details.

2. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state.

10.1.7 Quad Enable (QE)

The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad

operation. When the QE bit is set to a 0 state (factory default) the /WP pin and /Hold are enabled. When

the QE bit is set to a 1 the Quad IO2 and IO3 pins are enabled.

WARNING: The QE bit should never be set to a 1 during standard SPI or Dual SPI operation if the

/WP or /HOLD pins are tied directly to the power supply or ground.

10.1.8 Erase Suspend Status (SUS)

The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing a

Erase Suspend (75h) instruction. The SUS status bit is cleared to 0 by the Erase Resume (7Ah)

instruction as well as a power-down, power-up cycle.

- 13 -

Publication Release Date: August 19, 2009

Preliminary - Revision E

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