W77E532A40DL 查看數據表（PDF） - Winbond
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W77E532A40DL Datasheet PDF : 86 Pages
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W77E532/W77E532A
Slave Address
Bit:
7
6
5
4
3
2
1
0
Mnemonic: SADDR
Address: A9h
SADDR: The SADDR should be programmed to the given or broadcast address for serial port 0 to
which the slave processor is designated.
Slave Address 1
Bit:
7
6
5
4
3
2
1
0
Mnemonic: SADDR1
Address: Aah
SADDR1: The SADDR1 should be programmed to the given or broadcast address for serial port 1 to
which the slave processor is designated.
ROM Banking Control
Bit:
7
6
5
4
3
2
1
0
-
-
-
- EN128K DCP12 DCP11 DCP10
Mnemonic: ROMCON
Address: Abh
EN128K: On-chip ROM banking enable. Set this bit to enable APFLASH0 and APFLASH1 by banking
mechanism. The P1.x is selected to be the auxiliary highest address line A16.
DCP1x: A16 selection. By default, P1.7 is defined as A16.
A16
DCP12
DCP11
DCP10
P1.0
0
0
0
P1.1
0
0
1
P1.2
0
1
0
P1.3
0
1
1
P1.4
1
0
0
P1.5
1
0
1
P1.6
1
1
0
P1.7
1
1
1
ISP Address Low Byte
Bit:
7
6
5
4
3
2
1
0
A7
A6
A5
A4
A3
A2
A1
A0
Mnemonic: SFRAL
Address: Ach
Low byte destination address for In System Programming operations. SFRAH and SFRAL address a
specific ROM bytes for erasure, ٛ escription or read.
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Publication Release Date: November 19, 2007
Revision A9
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