W83195BG-118 查看數據表（PDF） - Winbond

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W83195BG-118

Clock Generator

Winbond 

W83195BR-118/W83195BG-118

STEPLESS FOR INTEL 915/945 CHIPSETS

7.15 Register 14: Control (Default: 10h)

BIT

NAME PWD

DESCRIPTION

TYPE

7 DRI_CONT 0 CPUT / SRCT / PCIE_T / DOT_T output state in during POWER R/W

DOWN assertion.

1: Driven (2*Iref), 0: Tristate (Floating)

CPUT / SRCT / PCIE_T / DOT_T output state in during STOP

Mode assertion.

1: Driven (6*Iref), 0: Tristate (Floating)

Complementary parts always tri-state (floating) in power down or

stop mode.

6

Reserved 0 Reserved

R/W

5 SPCNT [5] 0 Spread Spectrum Programmable time, the resolution is 280ns. R/W

4 SPCNT [4] 1 Default period is 11.8us

R/W

3 SPCNT [3] 0

R/W

2 SPCNT [2] 0

R/W

1 SPCNT [1] 0

R/W

0 SPCNT [0] 0

R/W

7.16 Register 15: SST Control (Default: ECh)

BIT

NAME PWD

DESCRIPTION

7

INV_CPU 1 Invert the CPU phase, 1: Default, 0: Inverse

6

Reserved 1 Reserved

5 SPSP_TYPE

4

Reserved

1 Spread spectrum implementation method

1 : Pendulum type

0 : Original

0 Reserved

3

Reserved 1 Reserved

2

Reserved 1 Reserved

1

Reserved 0 Reserved

0

Reserved 0 Reserved

TYPE

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

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