WM5621 查看數據表（PDF） - Wolfson Microelectronics plc
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WM5621 Datasheet PDF : 14 Pages
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WM5621L
Functional Description
DAC operation
Each of WM5621L's four digital to analogue converters
(DACs) are implemented using a single resistor string with
256 taps corresponding to each of the input 8-bit codes.
One end of a resistor string is connected to the GND pin
and the other end is driven from the output of a reference
input buffer. The use of a resistor string guarantees
monotonicity of the DAC's output voltage. Linearity depends
upon the matching of the resistor string's individual elements
and the performance of the output buffer. The reference input
buffers present a high impedance to reference sources.
Double Buffered Mode
In normal operation the EN signal is used to control the
latching of data. All DAC registers and all bits of the
control word (other than MODE) are double buffered, with
the second buffer only being enabled when the EN pin is
taken low. In this way it is possible to update any number
of DAC inputs at once by writing a 12-bit word to update
each DAC register, with EN held high for all writes. When
EN is pulled low at the end of the last write, all DAC inputs
are latched at the same time. Figure 3 shows DACs A
and B being written to in this way.
Each DAC has a voltage output amplifier which is
programmable for gains of x1 or x2 through the serial
This mode also allows multiple devices to be share DATA
and CLK lines by having only separate EN lines.
interface. The DAC output amplifiers feature rail to rail
output stages, allowing outputs over the full supply voltage
range to be achieved with a x2 gain setting and a VDD/2
reference voltage input. Used in this way a slight
degradation in linearity will occur as the output voltage
approaches VDD.
Control of the WM5621L is effected through a serial
interface using three dedicated pins, CLK, DATA and EN.
A fourth pin (HWACT) is used to control the power-down
controls to each of the 4 DACs.
Single Buffered Mode
If the device is to be operated in single buffered mode, the
EN pin should be tied high, and the interface is always
active. The first write to the device after power-on should
be a write to the control register to set the MODE bit high.
The double buffered action is not possible as all words
are latched across on the twelfth falling edge of CLK.
Loss of synchronisation may occur if glitches are present
on the CLK and DATA inputs, a condition which may
Serial Interface
occur at power-on. If this has happened it is possible to
regain synchronisation by clocking in at least 12 zeros
(see Figure 4).
The serial interface uses the CLK pin to clock in data words
presented serially on the DATA pin. The data words are
It is not possible to reset the MODE bit from 1 to 0.
5
12 bits long and are written to either a control register or
to one of the four DAC registers. When the EN pin is held
Operation of the device after any attempt to do this is
undefined.
low the serial interface is held in reset.
Figure 1 shows the format of the 12-bit data word transfer
into the WM5621L. DATA is clocked on the falling edge of
CLK. Every data word must start with a high start bit
(preceeding zeros are ignored). The second bit is the
register select bit which selects a write into either the
control register or one of the DAC registers. Table 1 shows
all valid write sequences.
DAC Registers
Each DAC register holds an 8-bit unsigned byte to
represent the DAC code. Table 1 indicates how these
bytes are clocked into the DAC registers, with D7 being
the most significant bit of the byte. These registers are
reset to 0 at power-on.
The serial interface can operate in one of two ways,
controlled by the setting of the MODE bit in the control
register. The MODE bit defaults to 0 on power up which sets
the device to work in a double buffered mode. When MODE
is set to 1, the device operates in a single buffered mode,
which can be controlled through only two pins (DATA and
CLK, EN held high).
Wolfson Microelectronics
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